CN100378977C - Semiconductor device without chip carrier and manufacturing method thereof - Google Patents

Abstract

A semiconductor device without a wafer carrier comprises a wafer, a plurality of conductive elements, which are electrically connected to the wafer; a first colloid, which is electrically connected to an external device through the connection of the conductive elements to the wafer, and the ends of each conductive element are coplanar with the outer surface of the first colloid, so as to provide a good processing plane for the semiconductor device of the present invention, thereby improving the processability and yield of the electrical connection with the external device; and a second colloid, which is formed on the non-active surface of the wafer, so as to form a structure protecting the wafer together with the first colloid. The present invention also provides a method for manufacturing a semiconductor device.

Description

Semiconductor device without chip carrier and manufacturing method thereof

The invention relates to a semiconductor device, especially a semiconductor device in which a chip is electrically connected to the outside by a plurality of conductive elements arranged in an array.

In order to meet the needs of electronic products, such as notebook computers (NB), personal digital assistants (PDA) mobile phones or set-top boxes, etc., in addition to relying on the improvement of component integration technology, it is also necessary to reduce the volume of the internal components themselves. Thickness, or weight should be considered accordingly. Therefore, for the semiconductor device, which is one of the core components of electronic products, effectively reducing the height and size of the device itself has become a major subject of joint research in the industry.

Although the current semiconductor device has developed a ball grid array semiconductor device (BGA Semiconductor Device) from the leadframe-based package (Leadframe-Based Package), and then further developed a CSP (Chip Scale Package) device from the ball grid array semiconductor device Remarkable results have been achieved in reducing the size of semiconductor devices, but there are still many problems to be solved in this CSP device. First of all, when the chip in the CSP device is still electrically connected to the substrate by bonding wires, the bonding wires radiate outwards from the periphery of the chip to the substrate, so that the height of the arc and the area occupied by the bonding wires on the substrate are equal. Form the limiting factors of this kind of CSP device on the overall height and planar size; The bump (Solder Bump) itself has a certain height, plus the height of the chip, the substrate, and the solder ball (Solder Ball) planted on the bottom of the substrate, often makes the overall height of the CSP device unable to be effectively reduced. Furthermore, the implementation of the flip-chip technology for the CSP device that electrically connects the chip and the substrate will increase the packaging cost, and the manufacturing process is complicated, so it is often impossible to obtain an ideal yield. In addition, the use of the substrate not only increases the overall height, but also due to the high manufacturing cost of the substrate, the cost of the CSP device cannot be effectively reduced. At the same time, in this kind of CSP device, the materials of the chip, the substrate and the colloid used to cover the chip have very different thermal expansion coefficients, so that the CSP device of this structure is easy to be used in the packaging process, reliability verification or actual use. During the change, a significant thermal stress effect is produced on the wafer, resulting in warping or delamination, which affects the reliability and usability of the finished product.

The purpose of the present invention is to provide a semiconductor device which can effectively thin the overall thickness and reduce the area, and can reduce the cost without the chip carrier.

The present invention also provides a manufacturing method of a semiconductor device that can perform electrical and functional testing at the wafer level, so that packaging and testing can be completed in the same manufacturing process.

The semiconductor device provided by the present invention includes a chip, which has an active surface (Active Surface) and a relative non-active surface (Non-active Surface) that are arranged with electronic components and electronic circuits; Conductive elements on the active surface, each of which is electrically connected to the chip, for the chip to form an electrical connection with the outside through the conductive elements; a first colloid formed on the active surface of the chip, used In order to airtightly isolate the active surface of the chip from the outside world, and cover each of the conductive elements, but make the end of each conductive element expose the first colloid, and make the end of each conductive element and the first colloid the outer surface is coplanar; and a second colloid formed on the non-active surface of the wafer.

The conductive element can be a connecting bump (Connecting Bump) made of copper, tin, its alloys or other conductive metals, so that the preset contact points ( Placememt Spot), each contact point is electrically connected with the electronic components and electronic circuits formed on the active surface, so after each connecting bump is placed on the opposite contact point, each conductive element is electrically connected to the The chip; the conductive element can also be generally solder balls made of conductive metals such as tin, so that the solder balls are planted on the active surface of the chip by known ball planting technology, so that the chip and each solder ball form electrical connections.

The method for manufacturing a semiconductor device provided by the present invention includes the following steps: (1) preparing a wafer, which has an active surface formed with electronic components and electronic circuits and an opposite non-active surface; (2) laying a plurality of The conductive element is connected to the preset contact point on the active surface of the wafer, so that the chip is electrically connected to the conductive element; (3) a first colloid is formed on the active surface of the wafer, and on the first After the colloid covers the conductive element, the end of each conductive element exposes the first colloid, and makes the end of the conductive element coplanar with the outer surface of the first colloid; (4) forming a second colloid on the on the non-active surface of the wafer; and (5) performing dicing to cut out the semiconductor device.

In order to reduce the overall height of the semiconductor device made by the above-mentioned method of the present invention, a horizontal polishing (Polishing) step can also be carried out after the step (3), so as to remove part of the first colloid and conductive elements to the second Until the colloid and the conductive element reach a predetermined thickness, this step can also flatten the co-constructed plane between the end of the conductive element and the outer surface of the first colloid, so as to provide its flatness. Simultaneously, after the horizontal grinding step, the non-active surface of the wafer can also be carried out a horizontal grinding step to reduce the thickness of the wafer; since the wafer industry provides good support for the first colloid, this horizontal grinding process will not cause damage to the wafer. Crack, which can further reduce the overall height of the finished semiconductor device. Similarly, after the second colloid in step (4) is formed, the second colloid can also be subjected to horizontal grinding treatment to effectively reduce the thickness of the second colloid.

The present invention has the following advantages: (1) the device of the present invention can effectively reduce the overall thickness of the device, and reduce the area; The electrical connection quality of the device; (4) the device has sufficient mechanical strength and can avoid warping or delamination; (5) the manufacturing process of the device is simplified and the cost is low.

The features and effects of the present invention will be further described in detail below with preferred specific embodiments in conjunction with the accompanying drawings.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention;

2 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention with a cooling fin attached to the second glue;

3 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention;

4A to 4G are schematic flowcharts of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

Description of component symbols

1, 2, 3 Semiconductor devices

10, 20, 30 chips

100, 200, 300 action surfaces

101, 301 Non-active surface

11 link bump

110, 210, 310 ends

12, 22, 32 first colloid

120, 220, 320 outer surface

13, 33 Second colloid

14 heat sink

21, 31 solder balls

P grinder

FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. As shown in the figure, the semiconductor device 1 includes a chip 10, which has an active surface 100 and an opposite non-active surface 101, and a plurality of contact points (not shown) are pre-formed on the active surface 100, so as to A plurality of connecting bumps 11 made of conductive metal are planted on the corresponding contact points by known printing methods; since each contact point has to be a bonding pad (Bond Pads) formed on the active surface 100 or through redistribution ( After Re-distribution), the connecting pads (Connecting Pads) are electrically connected with the corresponding pads by conductive traces (ConductiveTraces), so after the connecting bumps 11 are planted on the active surface 100 of the chip 10, the chip 10 An electrical connection relationship is formed with the connection bump 11 . The formation of the aforementioned solder pads or connection pads is a known technology, so it will not be illustrated and described in detail here.

In addition, on the active surface 100 of the wafer 10, a first colloid 12 made of commonly used resin compounds such as epoxy resin is formed, so that the active surface 100 of the wafer 10 is separated from the outside air by the formation of the first colloid 12. In order to prevent outside moisture or pollutants from intruding into the active surface 100 of the wafer 10 . The first colloid 12 is formed in such a way that each of the connecting bumps 11 is covered, and the end 110 of each connecting bump 11 is exposed to the first glue 12, and the end 110 of each connecting bump 11 is connected to the first glue. The outer surface 120 of the first colloid 12 forms a coplanar surface. In this way, the semiconductor device 1 can form an electrical connection relationship with an external device (not shown) such as a printed circuit board through the connecting bump 11, and because the outer surface 120 of the first glue 12 is connected to the end of the connecting bump 11 The plane formed by the portion 110 has good flatness, so that when the semiconductor device 1 is electrically connected to an external device by the known surface mount technology (SMT) or reflow technology (Reflow), each connecting bump 11 can be effectively It is connected with the corresponding connection elements on the external device to improve the connection quality; and because the thermal expansion coefficient of the first colloid 12 is not much different from that of the general external device (such as a printed circuit board), it is easy to carry out surface adhesion or reflow soldering. When operating to electrically connect the semiconductor device 1 and external devices, the influence of the difference in coefficient of thermal expansion (CTE Dismatch) can be greatly reduced. At the same time, since the end 110 of the connecting protrusion 11 is in a planar shape, it is also conducive to the effective contact between the test needle and the test needle during the test operation, thereby improving the accuracy of the test.

A second colloid 13 is formed on the non-active surface 101 of the wafer 10, so as to correspond to the first colloid 12 and sandwich the wafer 10 therebetween. This sandwich structure can provide proper support for the wafer 10, so that the wafer 10 can be properly supported in the absence of When the substrate or lead frame is used as a chip carrier, the semiconductor device 1 still has sufficient structural strength. And because the second colloid 13 and the first colloid 12 positioned on the top and bottom of the wafer 10 are formed from the same resin compound, the thermal stress produced by the two on the wafer 10 during the temperature cycle can be roughly offset, so that the semiconductor device 1 Warpage or delamination will not occur, and the yield and reliability of the finished product will be effectively improved.

Therefore, the semiconductor device 1 of the present invention can save the use of the substrate or the lead frame, so the manufacturing cost can be reduced, the manufacturing process can be simplified, the overall height can be reduced to meet the requirement of thinning, and the area of the device itself can be reduced to the same size as the wafer. 10 have the same size; at the same time, the packaged finished product can not only be directly connected to an external device, but also be externally connected to a substrate to become a semiconductor device with a flip-chip structure.

In order to further enhance the structural strength of the semiconductor device 1 and improve heat dissipation efficiency, a heat sink 14 can also be glued on the second glue 13 , as shown in FIG. 2 . Since the heat sink 14 is directly glued on the second colloid 13, its thickness, shape and size are not limited, and can be set according to actual needs.

FIG. 3 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention. The semiconductor device 2 of this second embodiment is substantially the same as the aforementioned first embodiment, except that it uses solder balls 21 to replace the connection bumps 11 used in the first embodiment, because the solder balls 21 are known Therefore, known ball planting techniques can be implanted onto the active surface 200 of the wafer 20 . In order to form an end 210 that exposes the first colloid 22 after the solder ball 21 is coated with the first colloid 22, and to make the end 210 flat, a part of the first colloid is removed by horizontal grinding. Colloid 22 and solder ball 21, so that the thickness of first colloid 22 after grinding and the height of solder ball 21 are all reduced, and form the state as shown in the figure, make the end 210 that solder ball 21 forms to expose first colloid 22 and coplanar with the outer surface 220 of the first colloid 22 .

4A to 4G are used to illustrate the manufacturing method of the semiconductor device of the present invention. Since the manufacturing method of the present invention is directly packaged on a wafer, in order to avoid confusion with the foregoing embodiments, new symbols are assigned to each component.

As shown in FIG. 4A, a wafer 30 having an active surface 300 and an opposite non-active surface 301 is prepared. The wafer 30 can be cut according to the positions indicated by dotted lines in the figure to form a plurality of wafer units.

As shown in FIG. 4B , a plurality of solder balls 31 are implanted onto the active surface 300 of the chip 30 by a known ball planting technique, so that each solder ball 31 is electrically connected to the chip 30 .

As shown in FIG. 4C, a first colloid 32 made of epoxy resin is formed on the active surface 300 of the chip 30 to airtightly isolate the active surface 300 from the outside world, and each solder ball 31 is covered. . The forming method can be carried out by general printing method or glue dispensing method.

As shown in Figure 4D, grind the first colloid 32 and the solder ball 31 horizontally with a grinding machine P, so that part of the first colloid 32 and the solder ball 31 are completely removed, and the thickness of the first colloid 32 and the solder ball The height of 31 is reduced to a preset value, so that after the grinding is stopped, the solder ball 31 forms an end 310 that exposes the first colloid 32, and makes the end 310 coplanar with the outer surface 320 of the first colloid 32 . However, in this step, when the solder ball 31 is replaced by the above-mentioned connecting bump, since the height of the connecting bump and the thickness of the first colloid can be controlled during the process, the grinding process can be omitted.

As shown in FIG. 4E, after the formation of the first colloid 32, sufficient support is provided for the crystal unit 30, and a grinding machine P is used to grind the non-active surface 301 of the wafer 30, so that the thickness of the wafer 30 is thinned. At the same time, the wafer 30 will not be cracked or the electronic components and electronic circuits on the active surface 300 will not be damaged, so that the overall height of the packaged finished product can be further reduced. However, this step can be omitted if the technology of the wafer manufacturing process is sufficient to control the formation of the wafer to a desired thickness or the thickness of the wafer will not affect the thinning of the finished product.

As shown in FIG. 4F, a second colloid 33 made of electric epoxy resin is formed on the non-active surface 301 of the wafer 30, and the thickness thereof is controlled to cooperate with the first colloid 32 to provide the wafer 30 Sufficient structural strength. However, if the formation of the second colloid 33 cannot be controlled at the desired thickness due to the material used or the manufacturing process, it can also be ground to make it thinner.

Finally, as shown in FIG. 4G , the structure composed of the electrical first glue 32 , the wafer 30 and the second glue 33 is longitudinally cut by a cutting machine from a predetermined position, so as to cut out a single semiconductor device 3 .

In addition, after the forming step of the second colloid 33 shown in FIG. 4F is completed, the structure composed of the first colloid 32, the wafer 30 and the second colloid 33 can be incompletely cut by a cutting machine from a predetermined position, Make the cutting depth of each kerf stop at the second colloid 33 and only cut the first colloid 32 and the wafer 30, or stop at the first colloid 32 and only cut the second colloid 33 and the wafer 30, and then you can Carry out electrical and functional tests on each semiconductor device 3 that has been incompletely singulated; at this time, since the chip units of each semiconductor device 3 that has been incompletely singulated are no longer connected, crosstalk interference will not be generated in the high-frequency test (Cross-Talk) and affect test reliability. Of course, before the second colloid 33 is formed on the non-active surface 301 of the wafer 30, the wafer 30 can be pre-cut. In this way, after the second colloid 33 is formed, there is no need to cut the first colloid 32 or the second colloid. Two colloids 33 can be directly used for high-frequency testing without crosstalk interference.

The above are only specific embodiments of the present invention, and any other equivalent changes or modifications made without departing from the spirit and technology of the present invention shall still fall within the scope of protection of this patent.

Claims (5)

1. a method for making of not having the semiconductor device of chip carrier is characterized in that this method comprises the following steps:

Prepare a brilliant unit, this crystalline substance unit has an action face (100) and a relative non-action face (101);

Lay a plurality of conducting elements (11) to the action face of this crystalline substance unit so that should crystalline substance unit and this conducting element (11) electrically connect;

Form one first colloid (12) on the action face (100) of this crystalline substance unit, make the action face (100) and extraneous airtight isolation of this crystalline substance unit, and in order to coat this conducting element (11);

Level is ground this first colloid (12) and conducting element (11), with the height of its conducting element of thickness (11) of reducing this first colloid (12), make the end of this conducting element (11) respectively expose outside this first colloid (12) and with outer surface (120) copline of this first colloid (12);

Level is ground the non-action face (101) of this crystalline substance unit, reducing the thickness of this crystalline substance unit, and promotes the flatness of this non-action face (101);

Form one second colloid (13) on the non-action face (101) of this crystalline substance unit; And

The structure that is made of first colloid (12), wafer (10) and second colloid (13) is cut to cut out this semiconductor device.

2. method for making as claimed in claim 1 is characterized in that, this conducting element (11) is the binding projection of being made by conductive metal.

3. method for making as claimed in claim 1 is characterized in that, this conducting element (11) is the soldered ball of being made by conductive metal (21).

4. method for making as claimed in claim 1, it is characterized in that non-action face (101) that this second colloid (13) is formed at wafer (10) goes up after, comprise that a pair of this second colloid (13) carries out the step that level is ground, to reduce the thickness of this second colloid (13).

5. after method for making as claimed in claim 1, its feature were that also this cuts single step, gluing one fin was to this second colloid (13).

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