TWI249823B - Semiconductor package and method for fabricating the same - Google Patents

Abstract

A semiconductor package is proposed, including: a chip having an active surface formed with electronic elements and electronic circuits thereon, and a non-active surface opposed to the active surface; a plurality of first conductive elements disposed on the active surface of the chip and electrically connected to the chip; a first encapsulant formed on the active surface of the chip, for hermetically encapsulating the active surface of the chip and the first conductive elements, allowing end portions of the first conductive elements to be exposed to outside of the first encapsulant, wherein the exposed end portions of the first conductive elements protrude from the first encapsulant, so as to prevent second conductive elements that are formed on the end portions of the first conductive elements, from coming into contact or short-circuited with each other caused by collapse of the second conductive elements during a reflow-soldering process; a plurality of second conductive elements deposited on the end portions of the first conductive elements, allowing the chip to be electrically connected to an external device by means of the first and second conductive elements; and a second encapsulant formed on the non-active surface of the chip, for cooperating with the first encapsulant to protect the chip from external moisture or contaminant, and to provide sufficient structural strength for the semiconductor package. A method for fabricating the foregoing semiconductor package is also provided.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a plurality of conductive elements arranged in an array are electrically connected to the outside. [Technical Description of the Invention]

In order to meet the needs of electronic products, such as notebook computers (NB), personal digital assistants (PDA) mobile phones or set-top boxes (Set Top Box), in addition to the improvement of component integration technology, Reduce the volume, thickness, or weight of the interior components themselves. Therefore, it is one of the major issues in the industry to effectively reduce the height and size of the device itself for a semiconductor device that is one of the core components of an electronic product. I

The current semiconductor device has developed a ball grid array semiconductor device (BGA Semiconductor Device) by using a lead frame-based package, and further developed a CSP (Chip Scale Package) by a ball grid array semiconductor device. The device has made the size reduction of the semiconductor device have achieved initial success, but there are still many problems still to be solved in the CSP device. First, when the wafer in the CSP device is still electrically connected to the substrate by the bonding wire, the bonding wire extends outward from the peripheral edge of the wafer to the substrate. 'The height of the wire arc and the area occupied by the bonding wire on the substrate. Both of them form a limiting factor in the overall height and planar size of the CSP device; and if the wafer in the CSP device is electrically connected to the substrate by Flip Chip technology, it is used to electrically connect the wafer and the substrate. The Solder Bump itself has a certain height, and the height of the wafer, the substrate and the Solder Ball implanted on the bottom of the substrate often makes this CSP

1249823 ——~~~~_______ ^____— V. INSTRUCTIONS (2) The overall height of the device cannot be effectively reduced. Furthermore, the use of flip chip technology to electrically connect the CSP device to the substrate and the substrate may result in an increase in the cost of the package due to the implementation of the flip chip technology, and the process is complicated, and the desired yield is often not obtained. In addition, the use of the substrate, in addition to causing an increase in the overall height, is complicated by the manufacturing cost of the composite substrate, and the cost of the CSP device cannot be effectively reduced. At the same time, in this kind of CSP device, the material of the wafer, the substrate and the colloid used to coat the wafer has a very different coefficient of thermal expansion (CTE), so that the CSP device of the structure is easy to be in the packaging process, reliability verification or practical use. The temperature change during the time has a significant thermal stress effect on the wafer, causing warpage or delamination, which affects the reliability and usability of the finished product. Further, a semiconductor device that does not require a substrate is further developed, such as a semiconductor device without a wafer carrier and a method for manufacturing the same, which is disclosed in the invention of the invention patent No. 161, which forms a colloid using the active and non-active surfaces of the wafer. Replacing the substrate to achieve the structural strength required to protect the wafer is a technique that has made significant progress in reducing the size of the semiconductor device. However, the structure and method of the semiconductor device are such that the end of the conductive element is formed on the surface of the wafer. The outer surface of the upper colloid is coplanar, and if a conductive medium such as a tin ball, a solder bump or a solder paste is implanted on the end of the colloid exposed to the conductive member, When the wafer is electrically connected to the external device by the conductive medium, it is easy for the end portion of the conductive member to be coplanar with the outer surface of the colloid partially covering the conductive member, and the conventional reflow operation is performed. Because of the lack of anchoring mechanism between the conductive medium and the end of the conductive element, the conductive medium may deviate from the preset position after collapse or hot melt, and the phase is generated. Another conductive medium

1249823 V. INSTRUCTIONS (3) The difference in the cohesive force of the touch or the connection is another device that produces the size of the uneven body, which cannot be connected, and the paradox guides how to overcome the conduction. [Summary of the Invention] The low-cost semiconductor of the present invention is free from warpage or delamination of the present invention. The reduced area of the present invention comprises a wafer, a surface (Active (Non-active conductive element, wafer) Conductive one formed in the crystal to cause a short circuit phenomenon, or due to the connection difference, the partial or complete absorption of the mutual traction effect and the phenomenon of 'consisting the conductive medium high external device via the conductive medium to the neighbors completely The problem of the mutual contact of the media is a purpose to provide a kind of avoidance problem in the connection quality of the junction or touch, and the semiconductor device. Another object is to provide a body device. ~ Another object is to provide a charging device A semiconductor device in which a phenomenon occurs is further provided to provide a device capable of having a conductor. It is disclosed and has a cloth Surface A Su Rface); the action of each of the conductive element and the conductive sheet is provided for the purpose of providing the electronic component with a relatively small amount of electrical conductivity disposed on the component and the first bonding of the wafer medium and the external surface. Make the match, lead to different degrees, and complete the situation. An important lesson is to improve the conductivity of the conductive wafer. The semiconductor and electronic surface wafers are electrically connected to form an electrical connection, and the dielectric is made of a dielectric conductive medium. Sexual connection, as the title. The quality is reduced in the interest of the dielectric and the parts and can avoid the thickness of the device and the function of the device is used on the surface for the connection; the wafer Φ

16575.ptd Page 9 1249823 V. Inventive Note (4) The surface of the action is airtightly isolated from the outside, and covers each of the conductive elements, but exposes the end of each conductive element to expose the first colloid, and The end of the conductive element is lower than the outer surface of the first colloid, a plurality of conductive medium disposed at the end of the conductive element; and/or a second colloid formed on the inactive surface of the wafer. The conductive element is a connecting bump made of copper, tin, an alloy thereof or other conductive metal, and is disposed on the active surface of the wafer by a conventional printing method. On the Placememt Spot, each of the contacts is electrically connected to the electronic component and the electronic circuit formed on the active surface, so that after each of the connecting bumps is disposed opposite to each other, the conductive elements are Electrically connected to the wafer. The conductive element is also generally made of a conductive ball made of a conductive metal such as tin. The solder ball is implanted onto the active surface of the wafer by a known ball-planting technique, and the wafer and each solder ball are formed. Electrically conductive relationship; the conductive medium may also be a soldering ball, a connecting bump or a solder paste, etc., which is conventionally connected to the end of the conductive element by a conventional brush or ball. The conductive medium is electrically connected to the wafer by a conductive member. The method for fabricating the semiconductor device provided by the present invention includes the following steps: preparing a wafer having an active surface on which an electronic component and an electron is formed and a non-active surface; and (2) routing a majority a pre-set contact point of the component to the active surface of the wafer to electrically connect the conductive element of the wafer J; (3) forming a _ colloid on the surface of the wafer, and the first colloid After covering the conductive element, the end of each of the conductive elements exposes the first colloid; (4) etching the conductive element

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5. The end of the invention (5) is such that it is lower than the outer surface of the first colloid to a predetermined depth; (5) a plurality of conductive medium is disposed on the end of the conductive member and (6) is cut to cut The semiconductor device is singly removed; before the (β) step of the above process, a step of forming a second colloid on the inactive surface of the wafer may be optionally added. In order to reduce the overall height of the semiconductor device fabricated by the above method of the present invention, a step of grinding (Grindi) μ is performed after the step (3) to remove a portion of the first colloidal electrical component to a predetermined value. After the thickness is increased, the thickness of the wafer can be reduced by the wafer; due to the wafer support, the horizontal polishing process does not further reduce the second colloid of the optional step to form a horizontal grinding process to effectively The second colloid is horizontally ground at the end of the first colloid, and the end surface of the first colloid is exposed lower than the surface of the first colloid 7 and the first colloid is defined to provide the conductive medium. During operation, due to the cohesive force generated by the conductive conductive medium anchored to the root in the cavity, a portion of the outer surface of the body may be collapsed and the conductive member is directed to the first colloid and guided. At the same time, the horizontal grinding step is performed on the surface at the horizontal grinding step to provide good adhesion to the first colloid, causing chip cracking and overall height of the conductor device. Similarly, the second colloid may have a lower second colloid thickness. Therefore, after the step, the step (4) is performed to etch the electrical component so that the conductive outer surface '俾 a recess from the end of the conductive component' can form a positioning effect. Therefore, the medium is formed by the cavity, and the portion is formed by the conductive medium toward the root portion to prevent the conductive medium from being exposed to the first glue or the hot melt and the external expansion to the adjacent guide.

1249823 V. INSTRUCTIONS (6) The problem of dielectric occurs, so that adjacent conductive materials do not touch each other, causing a short circuit or uneven size of adjacent conductive media. BRIEF DESCRIPTION OF THE DRAWINGS The features and effects of the present invention will be described in further detail in the preferred embodiments with reference to the accompanying drawings. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention; FIG. 2 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention with a heat sink attached to a second colloid; and FIG. 3 is a second embodiment of the present invention; A cross-sectional view of a semiconductor device according to an example; and FIGS. 4A to 41 are schematic flow charts showing a method of manufacturing the semiconductor device of the second embodiment of the present invention. As shown in Fig. 1, a cross-sectional view of a semiconductor device according to a first embodiment of the present invention is shown. As shown, the semiconductor device 1 includes a wafer 10 having an active surface 100 and an opposite non-active surface 101 on which a plurality of contacts (not shown) are pre-formed. For most of the connecting bumps 11 made of conductive metal, the bonding bumps 11 are implanted to the corresponding connecting points; since the respective connecting points are formed as bonding pads (Bond Pads) formed on the active surface 100 or After the re-distribution, the connecting pads are electrically connected to the corresponding pads by conductive traces, so the connecting bumps 11 are implanted on the active surface of the wafer 10 After the upper portion, the wafer 10 is electrically connected to the connecting bumps 11. The formation of the aforementioned pad or bonding pad is a known technique and will not be described or illustrated herein. Formed on the active surface 100 of the wafer 10,

16575.ptd Page 12 1249823 V. Description of invention (7)

The first colloid 12 made of a resin compound such as an epoxy resin is used to isolate the active surface 100 of the wafer 10 from the outside by the formation of the first colloid 12, thereby preventing external gas or pollutants from intruding into the wafer 10. The surface is on the 1QQ. The first colloid 12 is formed by coating each of the connecting bumps 11 and horizontally grinding to a predetermined thickness so that the end of the connecting bump 11 is coplanar with the first colloid outer surface 120, and then That is, the connecting bump 11 is etched so that the end of the connecting bump 1 1 is lower than the outer surface 1 2 0 of the first colloid 1 2 to form a recess 11 5 , which is conventionally implanted on the recess 11 5 The conductive medium 18 is formed by a ball, such as a solder ball, so that the conductive medium 18 is electrically connected to the connecting bump 11; due to the provision of the recess 115, the conductive medium 18 is formed to be anchored to the concave The root portion of the hole 115 is 18 〇, so that the conductive medium 18 is positioned on the first colloid 12, and the conductive medium 18 is formed with a root portion 180, and its own cohesive force is condensed toward the root portion 180, so that it is effectively reduced. The portion of the conductive medium 18 exposed on the outer surface 12 of the first colloid 12 is expanded to the extent of collapse during the zinc returning operation, and the adjacent conductive medium 18 can be effectively prevented from being short-circuited or adjacent to each other. The phenomenon that the size of the conductive medium 18 is not uniform ' makes the conductive medium 18 effective It is connected with the corresponding connecting component on the external device to improve the connection quality; and since the thermal expansion coefficient of the first colloid 12 is not much different from that of the general f device (such as a printed circuit board), the surface adhesion or back is implemented. When the soldering operation electrically connects the semiconductor device 1 to the external device, the influence of the difference in thermal expansion coefficient (CTE Dismatch) can be greatly reduced. At the same time, a second colloid 13 may be formed on the non-working surface 101 of the wafer 1 to sandwich the wafer 1 corresponding to the first colloid 12.

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V. INSTRUCTION DESCRIPTION (8) In the meantime, the sandwich structure provides further support for the wafer i. The semiconductor has enhanced structural strength without the use of a substrate or lead frame for the wafer carrier. And because the upper and lower bodies 13 and the first colloid 12 located on the wafer 1 are formed of the same resin compound, the thermal stress generated on the wafer 10 in the temperature cycle is substantially canceled, and the semiconductor device 1 does not warp or The phenomenon of delamination, so that the yield and reliability can be effectively improved. w • Small 4w % is resolved to the semiconductor device with a flip chip structure, and a substrate can be externally connected to become a device. Therefore, the semiconductor device 1 of the present invention can eliminate the use of the substrate or the lead frame, thereby reducing the manufacturing cost, simplifying the process, reducing the overall height and reducing the thickness, and reducing the area of the device itself to the wafer. The size of the 10 is the same; at the same time, the finished package can be directly connected to further improve the structural strength of the semiconductor device 1 and improve the heat dissipation efficiency. The composite heat sink is bonded directly to the non-active surface 101 of the wafer 10 (not As shown in the figure, or a heat sink 14 is adhered to the second colloid 13, as shown in FIG. Since the heat sink 14 is directly adhered to the inactive surface 101 or the second gel 13 of the wafer 10, the thickness, shape and size thereof are not limited, and may be set as needed. Fig. 3 is a view showing the semiconductor device of the second embodiment of the present invention. The semiconductor device 2 of the second embodiment is substantially the same as the first embodiment described above, except that the solder bumps 21 are used in place of the connecting bumps 11 used in the first embodiment, since the solder balls 21 are Conventional, the conventional ball placement technique is implanted onto the active surface 200 of the wafer 20. For this welding

16575.ptd Page 14 1249823 V. INSTRUCTION DESCRIPTION (9) The ball 21 is coated with the first colloid 22 to form an end portion 210 exposing the first colloid 22, and the portion is ground by horizontal grinding. The colloid 22 and the solder ball 21 are such that the thickness of the first colloid 22 after polishing and the height of the solder ball 21 are reduced to form a state as shown in the figure, so that the end of the solder ball 2 1 is exposed. A colloid 22 is formed in the same manner as the outer surface 220 of the first colloid 22, and the end portion 2 1 0 of the glow ball 2 1 is lower than the outer surface 220 of the first colloid 2 2 to form a recess 215. . 4A to 4G are diagrams for explaining the manufacturing method of the semiconductor device of the present invention. Since the manufacturing method of the present invention is directly packaged on a wafer, in order to avoid confusion with the foregoing embodiments, each component is marked with a new symbol / as shown in Fig. 4A, an active surface is prepared. And a wafer 30 opposite the non-active surface 301. The wafer 30 is formed by cutting a portion indicated by a broken line in the figure to form a plurality of wafer units. As shown in Fig. 4B, a plurality of first solder balls 31 are implanted on the active surface 300 of the wafer 30 by a conventional ball placement technique to electrically connect each of the first solder balls 31 to the wafer 30. As shown in FIG. 4C, a first colloid made of epoxy resin is formed "on the active surface 300 of the wafer 30 to provide strength to support the wafer 3 while simultaneously isolating the active surface 300 from the outside. And coating each of the first welding orders 31. The forming method is formed by a general printing method or dispensing. As shown in FIG. 4D, the first colloid μ and the solder balls are horizontally polished by a grinder p. 31, the portion of the first colloid 32 and the first solder ball 31 are ground to reduce the thickness of the first colloid 32 and the height of the first solder ball 31 to a pre*

16575.ptd Page 15 1249823 V. DESCRIPTION OF THE INVENTION (10) Value '俾 After the grinding is stopped, the first solder ball 31 is formed to expose the end portion 310 of the first colloid 32, and the end portion 310 is first The outer surface 32 0 of the colloid 32 is coplanar. However, in this step, when the first solder ball 31 is replaced by the above-mentioned connecting bump, since the process can control the thickness of the connecting bump at the time of formation and the thickness of the first colloid, the grinding process is performed. Not implemented. As shown in FIG. 4E, after the first colloid 32 is formed, the support of the crystal element 3 is sufficient, and the non-active surface 3〇1 of the wafer 3 is polished by a grinder P, so that the wafer 30 is obtained. The thickness is thinned, and the wafer 3 is not cracked or damaged by the electronic components and electronic circuits on the surface 300, so that the overall height of the finished package is further reduced. However, if the technique of the wafer process is sufficient to control the formation of the wafer at the desired thickness of the second wafer without affecting the thinning requirements of the finished product, then the second or the second is omitted. 7, as shown in FIG. 4F, a second colloid 33 made of epoxy resin is formed on the non-made 301 of the wafer, and the surface is controlled by the first colloid 32. With the cooperation, it can further strengthen the structural strength of 70% thick. However, if the material or process is used, the formation of 1 wafer 30 33 cannot be controlled at the desired thickness = dicolloid to be thinned.汲j ^ U grinding process as shown in Fig. 4G, the first solder ball 31 (or even the last part is etched so that the end of the first solder ball 31 ^ ^ dragon) creep: lower than the first - outer surface 32 of colloid 32. - Appropriately deep: even two: the end 315. Juice city into a pocket

1249823 V. INSTRUCTION DESCRIPTION (11) As shown in Fig. 4, the second solder ball 34 is implanted by conventional means to make the second connection relationship, and the crystal element 3 is not provided (not shown). connection. The ball placement technique forms a ball 34 on the recess 315 with the first solder ball 31. The second solder ball 34 and the external device. Finally, as shown in Fig. 41, the structure 3 is formed by the above steps. The slitting machine cuts the structure from the predetermined part to cut out the individual semiconductor package. The spirit and technology of this creation should not be included in the following patents. The specific embodiment of the component symbol description], the equivalent change or modification made by any other, guilty

1,2, 3 Semiconductor device 100, 200, 300 Active surface 11 Bonding bumps 12, 22, 32 First colloid 13, 33 First colloid 115, 215, 315 Cavity 21, 31 Solder ball 研磨 Grinder 1 0, 20, 30 Wafer 1 〇1,3 0 1 non-acting surface 110, 210, 310 end 1 20, 2 20, 320 outer surface 14 heat sink 18 conductive medium 34 second solder ball

Claims (1)

1249823 VI. Patent application scope 1. A semiconductor device comprising: a wafer having an active surface and an opposite non-acting surface; a plurality of conductive elements disposed on an active surface of the wafer and electrically connected to the wafer Connecting, a first colloid formed on the active surface of the wafer to hermetically isolate the active surface from the outside, and covering the conductive member, exposing the end of each conductive member to the first colloid and a surface of the first outer surface of the first adhesive; and a plurality of conductive materials disposed on the outer surface of the outer surface of the first adhesive to electrically connect the conductive member to the conductive member. The semiconductor device of item 1, further comprising a second colloid formed on an inactive surface of the wafer. 3. The semiconductor device of claim 1, wherein the semiconductor device is further provided with a heat sink attached to the second gel. 4. The semiconductor device of claim 1, wherein the conductive member is a bonding bump made of a conductive metal. 5. The semiconductor device of claim 1, wherein the conductive member is a solder ball made of a conductive metal. 6. The semiconductor device of claim 1, wherein the conductive medium is a solder bump made of a conductive metal. 7. The semiconductor device of claim 1, wherein the conductive medium is a solder ball made of a conductive metal. 16575.ptd Page 18 1249823 VI. Scope of Application Patent 8. The semiconductor device of claim 1, wherein the conductive medium is a solder paste. 9. The semiconductor device of claim 1, wherein the first colloid and the second colloid system are made of a resin compound. A method for fabricating a semiconductor device, comprising the steps of: preparing a wafer having an active surface and a relatively non-active surface; laying a plurality of conductive elements on the active surface of the wafer to The crystal element is electrically connected to the conductive element; forming a first colloid on the active surface of the crystal element, so that the active surface of the crystal element is hermetically isolated from the outside, and the conductive element is coated, but each Exposed at the end of the conductive element to expose the first colloid to be coplanar with the outer surface of the first colloid, and etch the exposed end of the conductive element so that the end of the conductive element is lower than the outer surface of the first adhesive to form a concave a plurality of conductive materials are disposed to the exposed ends of the conductive elements to electrically connect the conductive elements to the conductive medium; and the structure formed by the above steps is cut to sing out the semiconductor device. 1 1. The method of claim 10, wherein after the step of disposing the multi-conductive medium to the exposed end of the conductive element to electrically connect the conductive elements to the conductive medium, A step of forming a second colloid on the inactive surface of the wafer. 1 2 . The method of claim 10, wherein the conductive component is 16575.ptd Page 19 1249823 VI. Scope of application patents Coupling bumps made of conductive metal. The method of claim 10, wherein the conductive member is a solder ball made of a conductive metal. The method of claim 10, wherein the conductive medium is a solder bump made of a conductive metal. The method of claim 10, wherein the conductive medium is a solder ball made of a conductive metal. The method of claim 10, wherein the conductive medium is a paste made of a conductive metal. 1 7 . The method of claim 10, wherein after the first colloid is formed on the active surface of the wafer, a step of horizontally grinding the pair of the first colloid and the conductive member is performed to reduce the number The thickness of a gel and the height of the conductive element. 1 8 . The method of claim 17 of the patent application, after the horizontal grinding of the first colloid and the conductive element, comprises a step of horizontally grinding a pair of non-acting surfaces of the wafer to reduce the wafer thickness. 1 9 . The method of claim 11, wherein after the second colloid is formed on the non-active surface of the wafer, the step of horizontally grinding the pair of the second colloid is performed to reduce the second colloid thickness. 2 0. The method of claim 10, after the step of singulating, bonding a heat sink to the inactive surface of the wafer. 2 1. If the method of claim 11 is applied, after the step of singulation, a heat sink is adhered to the second gel. 16575.ptd Page 20