CN100361279C - A pre-cleaning process after etching silicon-containing low dielectric constant material - Google Patents

Abstract

The invention belongs to the technical field of semiconductor integrated circuit manufacturing technology, and in particular relates to a pre-cleaning process after SiLK etching. As device sizes get smaller, interconnect RC delays have an increasing impact on device turn-on speed. Copper and low dielectric materials are currently used to reduce RC interconnect delays. SiLK is a new low-dielectric material, but it still has some problems in process integration. The present invention improves and proposes a pre-cleaning process after SiLK etching, and the specific process is: the degassing chamber (CHC) of the SiLK silicon wafer device after etching; then the silicon wafer after degassing is entered into the pre-cleaning chamber (CHA), use Ar plasma to perform low-energy sputtering etching on the silicon wafer; finally, put the silicon wafer into the cooling chamber (CH1) and the barrier layer (CH2) chamber to deposit the barrier layer, such as Ti/TiN or Ta/ TaN.

Description

A pre-cleaning process after etching silicon-containing low dielectric constant material

technical field

The invention belongs to the technical field of semiconductor integrated circuit manufacturing technology, and in particular relates to a pre-cleaning process after etching of a silicon-containing low dielectric constant material (SiLK).

Background technique

With the continuous development of IC technology, the device size is getting smaller and smaller, and the interconnection RC delay has a greater impact on the device turn-on speed, far exceeding the impact of the gate delay, so reducing the RC interconnection delay has become the focus of attention. . In 1997, the IC industry began to use Cu with low resistivity to replace Al with high resistivity to reduce the interconnection resistance, and it was applied to the process of 0.22μm and below (although Cu is one of the metals that people are reluctant to introduce into the semiconductor production process, The main reason is that Cu will diffuse quickly in the silicon wafer and silicon dioxide medium, and the performance of the device will be unstable in case of contamination); on the other hand, people use low dielectric materials (k value is smaller than SiO ₂ ) to replace the traditional SiO ₂ , in order to reduce the interconnection intermetallic/layer capacitance C, and start to apply to the technology of 0.18μm and below. At the beginning, people used F-doped SiO ₂ --- FSG (k ~ 3.5, an improved SiO ₂ ) to apply to logic and storage devices manufactured by 0.18μm technology, such as CPU and DRAM/SRAM. When entering 0.13μm technology, people need materials with lower k value (k≤3). There are currently two methods for preparing low dielectric materials --- CVD and spin coating (Spin on), and both are used in the production line. CVD equipment manufacturers advocate low-dielectric materials made by CVD methods, such as Applied Materials and Novellus, which are developing products related to SiOC; while material suppliers advocate the use of spin-coating methods to prepare low-dielectric materials, such as SiLK is Dow The relevant characteristics of the products developed by Chemical Company are shown in the table below (from Dow chemical). If SiLK and Cu are applied to the subsequent interconnection process, the performance of the device is 37% higher than that of Al/SiO ₂ .

The following table is about the physical and electrical properties of SiLK materials (from Dow Chemical)

Dielectric constant k 2.62 leakage current   3.3×10^-10A/cm²@1MV/cm breakdown voltage 4MV/cm Glass transition temperature Tg ＞450℃ thermal stability ＞425℃ modulus of elasticity 2.7GPa Toughness   0.62MPa m^{1, 2} stress 45MPa

Humidity 0.25%@80%RH, 25℃ Thermal conductivity 0.18W/mK

However, when the SiLK material is applied to mass production, there are still some problems in the integration process with the copper process, such as the change of k value of SiLK, the choice of etching gas, the adhesion to the barrier layer, and the tolerance to the copper CMP process. wait. SiLK (k=2.7) is a new low-dielectric resin material. The problems existing in the process integration process of SiLK material and copper are currently being actively explored because it is a brand-new technical problem.

Contents of the invention

The present invention proposes a pre-cleaning process (mainly applied to the Damascus process module) after SiLK etching, with the purpose of: 1. In order to remove the residue after etching, such as the polymer after degumming remains on the side wall or bottom of the hole; 2. . Open up the SiC etch barrier layer whose bottom is not completely etched through by sputtering.

SiLK low dielectric material is a new spin-coating material developed by Dow Corning in the United States. However, there are many problems to be solved in copper single/double damascene process integration, such as the change of SiLKk value, hard mask selection, etch stop Layer selection, adhesion to copper barrier layer, tolerance to CMP process, selection of etching gas, cleaning of through holes after etching, etc.

The pre-cleaning process after SiLK etching proposed by the present invention is to use Ar plasma method to pre-clean the silicon wafer after SiLK etching. The specific steps are: put the etched SiLK silicon wafer into the degassing chamber (CHC) of the equipment for degassing process; then put the degassed silicon wafer into the pre-cleaning chamber (CHA) and treat it with Ar plasma. The silicon wafer is sputter etched to complete the pre-cleaning process.

In the present invention, the above-mentioned degassing process requires controlling the temperature of the silicon wafer to be 340-360° C., the time is 54-66 seconds, and the Ar gas flow is 12-18 sccm; the time for the above-mentioned low-energy sputtering etching or cleaning with Ar plasma for 24-36 seconds with a bias of 270-330V.

The present invention proposes a process—Ar plasma pre-cleaning (before the deposition of the copper barrier layer) aimed at the cleaning problem of the through hole after etching. By comparing the electrical measurement results and SEM/FIB micrographs with and without pre-cleaning process, it is concluded that this process improves the hole filling of metal and reduces the resistance of metal interconnection. Ar plasma not only removes the residue in the through hole, but also Ar ion sputtering makes the right angle of the through hole smooth (top and bottom), easy to fill in the hole. In addition, the SiC etch barrier layer at the bottom of the through hole in some areas is not completely etched through, and Ar ion sputtering during pre-cleaning can also partially or completely open it.

The invention has simple process, obvious effect and easy operation, and is very suitable for large production lines.

Detailed ways

The present invention will be specifically described below by way of examples.

1. Degassing (Degas) : Put the etched SiLK silicon wafer (such as a single damascene structure: 50nm SiC/500nmSiLK/50nm SiC/150nm SiO2) into the degassing chamber (CHC) of the Endural equipment, and continue at 350°C For 60 seconds, the Ar gas flow rate was 15 sccm.

2. Through-hole pre-cleaning : put the degassed silicon wafer into the pre-cleaning chamber (CHA), and use Ar plasma to perform low-energy sputtering etching on the silicon wafer to remove the residue in the through-hole for the next step of deposition Copper barrier preparation. The specific parameters of cleaning are as follows: cleaning (or etching) time: 30s; bias voltage: 300V; power of RF1 and RF2 are both 300W; Ar gas flow rate is 5 sccm.

3. Cooling and deposition of copper barrier layer : After the silicon wafer is cleaned, enter the cooling chamber (CH1) and the barrier layer (CH2) chamber to deposit barrier layers, such as Ti/TiN or Ta/TaN.

Claims (1)

1, the prerinse technology after a kind of SiLK dielectric materials etching, it is characterized in that carrying out prerinse with the silicon chip of Ar plasma method after to the SiLK etching, concrete steps are: the chamber that degass that the SiLK silicon chip after the etching the is put into equipment operation of degassing is handled; Silicon chip after will degassing then enters the prerinse chamber, with the Ar plasma silicon chip is carried out ise, finishes prerinse technology; Wherein, in the described operation of degassing, the control silicon temperature is 340-360 ℃, and the time is 54-66 second, and the Ar throughput is 12-18sccm; The described time of carrying out ise with the Ar plasma is 24-36 second, and bias voltage is 270-330V.