CN100353703C

CN100353703C - Reconfigurable linear feedback shifting register

Info

Publication number: CN100353703C
Application number: CNB2004100235484A
Authority: CN
Inventors: 刘志恒; 曲英杰; 丁勇; 何云鹏; 陈永强; 张世友
Original assignee: Hisense Group Co Ltd
Current assignee: Hisense Group Co Ltd
Priority date: 2004-01-29
Filing date: 2004-01-29
Publication date: 2007-12-05
Anticipated expiration: 2024-01-29
Also published as: CN1558590A

Abstract

The present invention relates to a reconfigurable linear feedback shifting register which belongs to a modular circuit of a reconfigurable cipher coprocessor. The reconfigurable linear feedback shifting register comprises a structural arrangement register and a feedback shift register, wherein the feedback shift register is composed of a shifting register and a feedback function circuit. The shifting register comprises n multiplexers and n D triggers which are respectively connected with a plurality of multiplexers. The feedback function circuit comprises m MUX, m-2 and gates and m-1 exclusive-OR gates, wherein the m-1 exclusive-OR gates are orderly connected with and last input to the multiplexer of NO. n-1, wherein m and n are both natural numbers. The present invention can ensure a cipher coprocessor circuit to realize different encryption and decryption algorithms, the difficulty of cryptanalysis (attack) is greatly increased and the security of a cryptographic system is enhanced. The present invention has the advantages of reconfigurability and simple structure, and can be widely used for reconfigurable cipher coprocessors.

Description

Reconfigurable linear feedback shift register

Technical Field

The invention belongs to a reconfigurable cipher coprocessor circuit in the field of information security, and particularly relates to an improvement of a reconfigurable linear feedback shift register module of the circuit.

Background

One of the most basic and effective measures for securing information is to perform a cryptographic transformation on the information. Cryptographic circuits are the most central basic components that make up cryptographic systems. For a special encryption circuit, since the hardware circuit structure is designed for a specific encryption/decryption algorithm, only one algorithm can be adapted, which greatly limits the application range.

The reconfigurable cipher circuit based on the reconfigurable cipher logic provides a new approach for data encryption, the reconfigurable characteristic of the internal circuit structure enables the architecture to have certain flexibility, and the problem that the architecture is not matched with different application requirements brought by the traditional rigid architecture is well solved. Compared with a special password circuit, the reconfigurable password coprocessor has the following advantages: (1) the user can realize various different cryptographic algorithms on the reconfigurable cryptographic coprocessor through programming according to own requirements, once the cryptographic algorithms need to be upgraded and updated, the cryptographic circuit does not need to be replaced, and only corresponding programming software needs to be modified, so that the method is very convenient, the service life of the cryptographic system can be prolonged, and the investment benefit of the user is protected; (2) the reconfigurable cipher coprocessor is not designed for a specific cipher algorithm, but is a general hardware implementation platform provided for a large number of cipher algorithms (mainly symmetric key system algorithms) with certain commonality, the reconfigurable cipher coprocessor does not contain specific cipher algorithm information before being put into use, and the implemented cipher algorithm is determined by a user through programming before use, so that the information of the cipher algorithm is not leaked in the design and production stages of a circuit, and the safety coefficient of the cipher system is improved; (3) the development cycle of the reconfigurable cipher coprocessor-based cipher system is shorter than that of a special cipher circuit. (4) The user can conveniently change the used cryptographic algorithm at any time, and the service cycle of the same cryptographic algorithm is shortened, so that the difficulty of cryptographic analysis (attack) is greatly increased, and the security of the cryptographic system is improved from another aspect.

Feedback shift registers are the main components in the construction of sequential cipher algorithms, often used to generate pseudorandom sequences. The stage number, the feedback tap and the feedback function of the invention are all variable, thereby meeting the requirements of different encryption and decryption algorithms.

Disclosure of Invention

The invention aims to overcome the defects and shortcomings, and provides a password system which can prolong the service life of the password system and protect the investment benefit of users; the information of the cryptographic algorithm cannot be leaked in the design and production stages of the circuit, so that the safety coefficient of the cryptographic system is improved; the user can conveniently replace the used cryptographic algorithm at any time, and the service cycle of the same cryptographic algorithm is shortened, so that the difficulty of cryptographic analysis (attack) is greatly increased, and the safety of the cryptographic system is improved from another aspect.

In order to solve the technical problems, the invention adopts the following technical scheme:

a reconfigurable linear feedback shift register comprises a structure configuration register and a feedback shift register connected with a control signal output end of the structure configuration register, wherein the feedback shift register consists of a shift register and a feedback function circuit; the shift register comprises a multiplexer and a D trigger, the number of the multiplexers and the D trigger is the same as the number of bits of initial data to be loaded, and each bit of data needs to use one multiplexer and one D trigger; the output end of the multiplexer is connected with the input end of the D trigger, the first input end of the multiplexer receives one-bit initial data, the second input end of the multiplexer is connected with the output end of the next-bit D trigger, and the second input end of the last multiplexer is connected with the output end of the feedback function circuit; the gating control end of the multiplexer receives the initial data loading/feedback shift control signal and selects the data output of the first input end or the second input end; the feedback function circuit comprises multiplexers, AND gates and XOR gates, wherein the number of the multiplexers is the same as that of feedback tap control signals output by the structure configuration register and is m, the number of the XOR gates is (m-1), and the number of the AND gates is the same as that of feedback coefficient control node signals output by the structure configuration register and is (m-2); the input ends of the multiplexers are respectively connected with the output ends of the D triggers, and the gating control ends respectively receive one path of feedback tap control signals output by the structure configuration register and select one path of input end data to output; wherein the multiplexer MUX₀And multiplexer MUX_m-1Is directly XOR-ed with the XOR gate₁And XOR gate_m-1WhereinMultiplexer MUX with one input end connected one to one and middle₁～MUX_m-2The output ends of the AND gates are respectively and correspondingly connected with one input end of the (m-2) AND gates, the other input end of the AND gate respectively receives the (m-2) feedback coefficient control node signals output by the structure configuration register, and after the AND operation, the AND gate is respectively XOR-connected with the XOR gate₁～XOR_m-2The input ends of the exclusive or gates XOR are connected one to one₂～XOR_m-1The other input end of the first path of the input end of the second path₁～XOR_m-2The output of the exclusive or gate XOR_m-1The output end of the feedback function circuit is the output end of the feedback function circuit and is output to the shift register; wherein m is a natural number greater than 1.

The bit number of the initial data is variable between 2 and 32; in the present invention, the initial data includes 32 bits, and thus, a 32-way multiplexer and a 32-way D flip-flop are included in the shift register. The number of feedback tap control signals output by the structure configuration register is between 2 and 6. In the invention, the number of the feedback tap control signals is set to be 6, and the number of the feedback coefficient control node signals is set to be 4.

The linear feedback shift register used by different cryptographic algorithms has different stages, feedback taps and feedback functions. In order to match different algorithms, the circuit structure (number of stages, feedback taps, feedback functions) of the linear feedback shift register must be variable, and we call such a linear feedback shift register a reconfigurable linear feedback shift register. Below we present one principle of a reconfigurable linear feedback shift register over GF (2), which is equally applicable to a reconfigurable linear feedback shift register over GF (2 n).

In order to realize the reconfigurability of the cipher coprocessor, the requirements of various encryption and decryption algorithms are met. The present invention provides a linear feedback shift register whose number of stages, feedback taps, and feedback function are all variable.

The linear feedback shift register is composed of a shift register and a feedback function. Let the shift register be composed of n D flip-flops, and take m of them as feedback taps.

To achieve reconfigurable characteristics, in the circuit of the feedback shift register, 3 controllable nodes are provided:

a feedback tap selects a control node;

a feedback coefficient control node;

the D flip-flop inputs the source control node.

The control codes of the controllable nodes are stored in the configuration register, and the stage number, the feedback tap and the feedback function of the feedback shift register can be changed by rewriting the value of the configuration register through an instruction, so that the feedback shift registers with different structures are realized.

The task of the present invention is thus accomplished.

The invention can ensure that the cipher coprocessor circuit realizes a plurality of different encryption and decryption algorithms, greatly increases the difficulty of cipher analysis (attack), and improves the safety of the cipher system. The device has reconfigurability and a simple structure. The method can be widely applied to reconfigurable password coprocessors.

Drawings

FIG. 1 is a block diagram showing the structure of embodiment 1 of the present invention;

FIG. 2 is a schematic circuit diagram thereof;

fig. 3 is a signal side definition of a 32-bit reconfigurable feedback shift register.

Detailed Description

Example 1. A reconfigurable linear feedback shift register is shown in figures 1 and 2. This is a 32-bit reconfigurable feedback shift register. It includes a configuration register 1 with CLK, RST, E and CONT [33:0] inputs and CR [33:0] outputs and a feedback shift register 2 with CR [33:0] inputs and CLK, RST, OP, LOAD and D [31:0] outputs and Q [31:0] outputs. The feedback shift register 2 is composed of a shift register and a feedback function circuit.

The shift register comprises input terminals D [31:0] respectively]N multiplexers for LOAD, n D flip-flops connected to the n multiplexers, respectively, the feedback function circuit includes outputs of the n D flip-flops and an output CR [33:0] of the configuration register 1]M MUXs (MUXs) with feedback tap control signals as input terminals₀～MUX_{m_1}) Respectively using MUX₁～MUX_{m_2}And CR [33:0]FBC [1 ]]～FBC[m-1]M-2 AND gates as input end, and MUX₀And MUX₁Connected exclusive OR gates XOR₁XOR gate connected with m-2 AND gates in turn₂～XOR_{m_2}And MUX_{m_1}Connected exclusive OR gates XOR_{m_1}M-1 exclusive-OR gates are sequentially connected and finally input to the n-1 st multiplexer, and m and n are natural numbers.

The stage number n of the 32-bit reconfigurable linear feedback shift register is variable between 2 and 32, and the number m of feedback taps is variable between 2 and 6. Any one of 32 registers can be selected for each feedback tap, and any linear feedback function of 2-6 feedback taps can be realized. Specifically, it can realize the following 4 operations: the method comprises the steps of resetting operation, structure configuration register writing operation, initial data loading operation and feedback shifting operation. The specific operation is as follows:

(1) resetting operation:

when the RST is equal to 1 when the clock rising edge arrives, all values of the configuration register and the shift register of the reconfigurable feedback shift register are set to 0. The reset operation is synchronized with the clock CLK.

(2) Architectural configuration register write operation:

when the clock rising edge arrives, if E is 1, the configuration data CONT [33:0] is written to the configuration register CONTREG. The structure configuration register is used for storing structure control data of the reconfigurable feedback shift register, and the values of the structure configuration register are as follows:

CR[33:0]＝{FBC，TAPSEL5，TAPSEL4，TAPSEL3，TAPSEL2，TAPSEL1，TAPSEL0}

the linear reconfigurable feedback shift register comprises a linear reconfigurable feedback shift register and a linear reconfigurable feedback shift register, wherein TAPSELj (j is 0, 1, 5) is a feedback TAP control signal of the linear reconfigurable feedback shift register, TAPSELj (k is 0, 1, 5, k is 0-31) indicates that the output of a kth D flip-flop Dk is selected by the jth feedback TAP of the linear reconfigurable feedback shift register, the arrangement sequence of the feedback TAPs is sequentially TAP 0-TAP 5 from right to left, and the arrangement sequence of the D flip-flops is sequentially D0-D31 from right to left; the FBC is a feedback coefficient control node of the linear feedback shift register, and is used for determining a linear feedback function of the reconfigurable feedback shift register:

F＝TAP0^(FBC[1]&TAP1)^(FBC[2]&TAP2)^(FBC[3]&TAP3)^(FBC[4]&TAP4)^TAP5

wherein ^ represents XOR operation, and & represents AND operation.

(3) Initial data load operation:

when the clock rising edge arrives, if OP is 1 and LOAD is 1, the initial data D [31:0] is loaded into the shift register. Wherein, the OP is an operation enabling control signal of the linear feedback shift register, and is used for controlling whether the reconfigurable feedback shift register works or not: when the OP is 1, the reconfigurable feedback shift register is in a working state, and when the OP is 0, the reconfigurable feedback shift register is in a closed state; the LOAD is an initial data LOAD/feedback shift control node of the linear feedback shift register, and is used for determining the operation type of the reconfigurable feedback shift register: LOAD of 1 indicates that the LOAD initial data operation is performed, and LOAD of 0 indicates that the feedback shift operation is performed.

(4) Linear feedback shift operation:

after the structural configuration of the reconfigurable linear feedback shift register and the initial data loading are completed, the linear feedback shift operation can be carried out. Let OP be 1 and LOAD be 0, then the reconfigurable feedback shift register feedback-shifts each cycle once, i.e. shifts out the rightmost 1 bit, and supplements the output of the linear feedback function to the leftmost 1 bit.

Embodiment 1 can ensure that the cipher coprocessor circuit realizes a plurality of different encryption and decryption algorithms, greatly increases the difficulty of cipher analysis (attack), and improves the security of the cipher system. The device has reconfigurability and a simple structure. The method can be widely applied to reconfigurable password coprocessors.

Claims

1. A reconfigurable linear feedback shift register, characterized by: the feedback shift register is composed of a shift register and a feedback function circuit; wherein,

the shift register comprises a multiplexer and a D trigger, the number of the multiplexers and the D trigger is the same as the number of bits of initial data to be loaded, and each bit of data needs to use one multiplexer and one D trigger; the output end of the multiplexer is connected with the input end of the D trigger, the first input end of the multiplexer receives one-bit initial data, the second input end of the multiplexer is connected with the output end of the next-bit D trigger, and the second input end of the last multiplexer is connected with the output end of the feedback function circuit; the gating control end of the multiplexer receives the initial data loading/feedback shift control signal and selects the data output of the first input end or the second input end;

the feedback function circuit comprises multiplexers, AND gates and XOR gates, wherein the number of the multiplexers is the same as that of feedback tap control signals output by the structure configuration register and is m, the number of the XOR gates is (m-1), and the number of the AND gates is the same as that of feedback coefficient control node signals output by the structure configuration register and is (m-2); the input ends of the multiplexers are respectively connected with the output ends of the D triggers, and the gating control ends respectively receive one path of feedback tap control signals output by the structure configuration register and select one path of input end data to output; wherein the multiplexer MUX₀And multiplexer MUX_m-1Is directly XOR-ed with the XOR gate₁And XOR gate_m-1One of the input ends of the multiplexer MUX is connected one to one, and the multiplexer MUX in the middle₁～MUX_m-2The output ends of the AND gates are respectively and correspondingly connected with one input end of the (m-2) AND gates, the other input end of the AND gate respectively receives the (m-2) feedback coefficient control node signals output by the structure configuration register, and after the AND operation, the AND gate is respectively XOR-connected with the XOR gate₁～XOR_m-2The input ends of the exclusive or gates XOR are connected one to one₂～XOR_m-1The other input end of the first path of the input end of the second path₁～XOR_m-2The output of the exclusive or gate XOR_m-1The output end of the feedback function circuit is the output end of the feedback function circuit and is output to the shift register; wherein m is a natural number greater than 1.

2. The reconfigurable linear feedback shift register of claim 1, wherein: the bit number of the initial data is between 2 and 32.

3. The reconfigurable linear feedback shift register of claim 2, wherein: the initial data includes 32 bits, and includes 32-way multiplexers and 32-way D flip-flops in the shift register.

4. The reconfigurable linear feedback shift register of claim 1, wherein: the number m of feedback tap control signals output by the structure configuration register is between 2 and 6.

5. The reconfigurable linear feedback shift register of claim 4, wherein: the number of the feedback tap control signals is 6, and the number of the feedback coefficient control node signals is 4.