CN100353351C - Signal encoding method for reducing serial ATA split physical layer pin count - Google Patents

Abstract

The invention relates to a signal coding method capable of reducing the pin number of a tandem ATA separated entity layer, which is characterized by comprising the following steps: a status signal encoder and a control signal decoder are arranged in the serial ATA separating entity layer, wherein the status signal encoder is connected with the storage medium controller through a parallel signal receiving line, the control signal decoder is connected with the storage medium controller through a parallel signal transmitting line, when data signals are transmitted among the status signal encoder, the control signal decoder and the storage medium controller, the control signals from the storage medium controller are encoded in the data signals by the control signal encoder at the storage medium controller end and decoded by the control signal decoder, and the ready status from the serial ATA separating entity layer is encoded in the data signals by the status signal encoder, thereby reducing the connected pins.

Description

Signal encoding method for reducing serial ATA split physical layer pin count

technical field

The present invention relates to a signal encoding method of circuit structure of ATA interface, in particular to a signal encoding method capable of reducing the number of serial ATA separation physical layer pins.

Background technique

In recent years, due to the high development of information-related industries and people's increasing requirements for computing and transmission speeds of information products, the industry has been continuously devoting itself to the development of various transmission interface specifications. As far as storage interfaces are concerned, the earliest transmission rate is 16MBps ATA (Advanced Technology Attachment) interface, through continuous improvement, the ATA33 interface with a transmission rate of 33MBps (mega byte per second), the ATA66 interface with a transmission rate of 66MBps, and even the interface specifications such as ATA100 and ATA133, but because the above-mentioned interface specifications are parallel ( Parallel) data transmission mode transmission, not only the number of signal lines required for transmission is large, but the noise interference is large, the length of the transmission line is greatly limited, and it is difficult to increase the transmission rate.

Recently, due to the continuous attempts and development of various companies, the serial ATA interface specification has finally been released, which not only increases the transmission rate to more than 1.5Gbps (giga bitper second) of the first generation, but also the 3.0 of the second generation in the future. Gbps and the third-generation 6.0Gbps are just around the corner, and the transmission of data only needs four signal lines, and the length of the signal lines can be greatly increased, which is a major breakthrough.

However, the current serial ATA interface specification products are still in the development stage, and parallel ATA products are still the mainstream in the market. In order to take into account the scalability and applicability, the industry still supports two interface specifications at the same time in the design of the computer system Mainly.

The solution adopted by some industry players is as shown in FIG. 1 , which is mainly to add a serial ATA physical layer (physical layer PHY) 123 in the storage media controller 121 of its main control chip 12 (such as the south bridge chip), A Serial ATA device 16 (such as a Serial ATA hard disk) can be connected through the Serial ATA physical layer 123, and the storage media controller 121 is connected to a Parallel ATA device through an IDE bus 14 18 (such as parallel ATA hard disk). Although such a structure can support serial ATA devices and parallel ATA devices at the same time, however, the serial ATA physical layer 123 needs to occupy a relatively large area because it is mainly composed of high-frequency analog circuits, and it is desired to integrate it into the main control In the chip 12, the area of the main control chip 12 will be too large, and the yield rate of its manufacture and production is difficult to control.

Therefore, how to propose a novel solution to the shortcomings of the above-mentioned conventional circuit architecture and the problems that occur during use, and design a simple and effective circuit structure, which can not only reduce the number of pins required for connection, but also ensure that the main Controlling the pass rate of chips and effectively reducing costs has long been the difficulty that users have longed for and that the inventor wants to solve. Based on years of experience in research, development, and sales in the information industry, the inventor Experience, thinking and improvement ideas, after many designs, discussions, trial samples and improvements, finally researched a circuit structure and signal encoding method that can reduce the number of serial ATA split physical layer interface signals, in order to solve the above The problem.

Contents of the invention

The technical problem to be solved by the present invention is to provide a tandem type that can not only reduce the number of pins required for connection, but also ensure the pass rate of the main control chip and effectively reduce the cost. The signal encoding method of the ATA split physical layer interface signal number.

The above technical problems of the present invention are achieved by the following technical solutions.

A circuit structure capable of reducing the number of serial ATA split physical layer interface signals, characterized by comprising:

A parallel-to-serial converter, including a parallel-to-serial converter and a serial-to-parallel converter, is respectively connected to a storage media controller by using a set of parallel signal sending lines and a set of parallel signal receiving lines for to convert the parallel signal from the storage medium controller into a serial signal, and convert the serial signal into a parallel signal for transmission to the storage medium controller;

A phase-locked loop, comprising a sending phase-locked loop connected to the parallel-to-serial converter and a receiving phase-locked loop connected to the serial-to-parallel converter, connected to the parallel-to-serial converter for Generate a clock signal required for data signal transmission, and transmit a reference clock signal to the storage medium controller;

At least one transmitter is connected to the parallel-to-serial converter, and each transmitter can convert serial data signals to a serial ATA device connected to it through a set of serial signal transmission lines;

At least one receiver is connected to the serial-to-parallel converter, and each receiver can transmit the data signal received from the connected serial ATA device to the serial-to-parallel converter through a set of serial signal receiving lines , and the serial-to-parallel converter converts the data signal into a parallel signal before sending it to the storage media controller; and

At least one OOB signal detector is connected to the receiving signal line of each corresponding receiver to detect the operation status of the serial ATA device, and can send multiple groups of detected signals to the storage media controller .

The circuit structure, in addition to the above-mentioned necessary technical features, can also add the following technical content during the specific implementation process:

When the controller and the transmitter or/and receiver have a one-to-two correspondence, there are also two active slave selectors, which can receive the control signal from the storage media controller and select the active or slave transmission line:

One of the active slave selectors is connected to each transmitter, and the corresponding transmitters can be respectively activated after receiving the transmission enable signal of the parallel-to-serial converter;

Another active slave selector can transmit the data signal corresponding to the receiver to the serial-to-parallel converter.

Wherein the parallel-to-serial converter and the serial-to-parallel converter in the parallel-to-serial converter are divided into two independent modules or integrated into a combined module.

A transmitting phase-locked loop and a receiving phase-locked loop in the phase-locked loop are divided into two independent modules or integrated into a combined module.

It also includes a power controller, which can receive multiple sets of control signals from the storage media controller to control its reset and other power states, and can send a physical layer ready status signal to the storage media controller.

Wherein the power control signal and the physical layer ready status signal are a multi-level status signal.

The physical layer ready signal includes a transmit ready signal and a receive ready signal from the phase locked loop.

It also includes a control signal decoder connected to the parallel signal sending line, which can decode a parallel signal including sending valid signals, and transmit the decoded sending valid signals and parallel data signals to the parallel-to-serial converter respectively.

It also includes a state signal encoder, which is connected to the serial-to-parallel converter to encode the converted parallel data signal and the received static signal from the OOB signal detector, and then transmit it to the storage medium control via the parallel signal receiving line device.

It also includes a transmission path controller, which is connected to each transmitter and each receiver, and can control the transmission path of the data signal according to the control signal of the storage media controller.

It also includes a selector, which is connected to each OOB signal detector, and can be selected to transmit the static signal received by one of the OOB signal detectors to the status signal encoder according to the control signal of the storage media controller.

The phase-locked loop has the function of switching and selecting multiple transmission rates, and switches operations by receiving a control signal from a storage medium controller through a signal line.

The present invention also provides a technical solution for the signal encoding method of the above-mentioned circuit.

A signal encoding method that can reduce the number of serial ATA separation physical layer pins is characterized in that a state signal encoder and a control signal decoder are set in the serial ATA separation physical layer, wherein the state signal The encoder is connected to the storage medium controller through a parallel signal receiving line, and the control signal decoder is connected to the storage medium controller through a parallel signal sending line, and data signals are transmitted between the state signal encoder, the control signal decoder and the storage medium controller When the control signal from the storage media controller is encoded in the data signal by the control signal encoder at the storage media controller end, it is decoded by the control signal decoder, and the ready status from the serial ATA split physical layer is obtained by A status signal encoder is encoded in the data signal, thereby reducing the number of connected pins.

In the specific implementation process of this coding method, the following technical content can also be added:

Wherein, if the data signal is transmitted from the storage media controller to the serial ATA split physical layer, the control signal encoder at the storage media controller end can send all the data as 0 or all as 1 in the falling interval of sending valid signals. Instead, it is decoded by a control signal decoder.

Wherein if the data signal is transmitted from the serial ATA split physical layer to the storage media controller, the status signal encoder can replace all the data with 0 or all 1 during the rising interval of the received static signal.

The advantages of the present invention are:

1. It is applied to the control chip with separate design of digital and analog. Under this design framework, the high-frequency analog circuit is fabricated in a separate physical layer chip, while the digital circuit part can be integrated in the storage media controller. Through appropriate Signal encoding can effectively reduce serial ATA split physical layer interface signals.

2. The main control chip can transmit the control signal to the physical layer chip with a multi-level signal, and the physical layer chip can also transmit the status signal to the main control chip with a multi-level signal.

3. A signal encoder and a signal decoder are used to encode the control signal and status signal into the data signal, so as to reduce the number of pins required for connection.

4. Utilize the characteristics of signal coding, and replace the original data signal with a special code that does not conform to the normal data coding, so as to identify the identifier.

In order to have a further understanding and understanding of the characteristics, structure and achieved effects of the present invention, I would like to provide a better implementation illustration and a detailed description, as follows:

Description of drawings

FIG. 1 is a block diagram of a conventional ATA interface architecture.

FIG. 2 is a circuit block diagram of a preferred embodiment of the present invention.

FIG. 3 is a circuit block diagram of another embodiment of the present invention.

FIG. 4 is a timing diagram of multi-level power supply control signals in the present invention.

FIG. 5 is a timing diagram of the physical layer ready status signal of the present invention. and

FIG. 6 and FIG. 7 are schematic diagrams of timing diagrams for decoding the sending valid signal and encoding the receiving static signal, respectively, according to the present invention.

Detailed ways

First, please refer to FIG. 2 , which is a circuit block diagram of a split physical layer chip according to a preferred embodiment of the present invention. As shown in the figure, its main structure includes: a parallel serial converter (serialize/deserializer; SerDes), a phase locked loop (phase locked loop; PLL), at least one transmitter (transmitter) 405, at least one receiver A receiver 407 and at least one OOB signal detector 461 .

The components required for the tandem ATA physical layer under the framework of the present invention are designed in two chips according to the circuit characteristics. The separate physical layer chip 40 includes all high-frequency analog circuits, and the other physical layer circuits are digital. The main circuit is integrated in the storage media controller, such as the encoder (8B10Bencoder) that converts the 8bits signal and control signal of parallel ATA into 10bits signal and converts the 10bits signal from serial ATA signal into 8bits signal and control Signal decoder (10B8Bdecoder) and character locator (word alignment), etc. In this way, the main control chip will not increase the chip area due to the integration of high-frequency analog circuits, and its production yield can be maintained, and the number of pins required for the connection between the main control chip and the serial ATA separation type physical layer 40 can also be reduced. reduce.

In this embodiment, the parallel-serial converter includes a parallel-to-serial converter (serializer; PISO) 423 and a series-to-parallel converter (deserializer; SIPO) 443, and the phase-locked loop also includes a transmit lock A phase loop 421 and a receiving phase-locked loop 441, wherein the transmitting phase-locked loop 421 can generate the clock signal required by the serial ATA split physical layer 40 to send the signal, and transmit the clock signal to the parallel-to-serial Column conversion 423 and storage media controller as its reference clock signal (RefCIK). The parallel-to-serial conversion 423 is based on the sending valid signal (TxValid) and the sampling clock signal (strobe differential clock; TxStrobe, TxStrobe) from the storage medium controller. The data signal to be transmitted is converted into a serial ATA data signal (TxData), and transmitted to the serial ATA device through a set of serial signal transmission lines (TXP1, TXN1 or TXP2, TXN2) by the transmitter 405 .

In the receiving part, the receiver 408 receives the signal from the serial ATA device through a set of serial signal receiving lines (RXP1, RXN1 or RXP2, RXN2) and then sends it to the serial-to-parallel converter 443, and the serial The serial-to-parallel converter 443 converts the serial signal into a parallel signal according to the clock signal generated by the receiving phase-locked loop 441, and converts the serial signal into a parallel signal through a set of parallel signal receiving lines (RxData[4; 0]) and two sampling clocks The pulse signal line (RxSTrob, RxSTrob-) transmits the data signal and sampling clock signal to the storage media controller. In addition, there is at least one OOB signal detector (out of and signal detector) 461 connected to each serial signal receiving line to detect the state of signal transmission, and will receive the squash signal (Squelch), initialization signal (Commlnit ) and a wake-up signal (ComWake) are sent to the storage media controller.

Furthermore, in this embodiment, because two groups of transmitters and receivers are included, an active serial ATA hard disk and a slave serial ATA hard disk can be connected at the same time, so an active slave selector (master) is also provided in the device. /slave selector) 425 and 445, which can receive the control signal (Master) from the storage media controller to select the active or slave transmission line. The active slave selector 425 is connected to each transmitter 405 and can respectively enable (enable) the corresponding transmitter 405 after receiving the transmit enable signal (TxEnable) from the parallel-to-serial converter 423 . Another active slave selector 445 can transmit the data signal (RxData) corresponding to the receiver 407 to the serial-to-parallel converter 443 .

In order to reduce the number of pins connecting the serial ATA split physical layer 40 and the storage media controller, a selector 403 can be added in the device, and the corresponding OOB signal can be detected according to the control signal (Master). The received quiet signal (SigQuiet) of the device 461 is sent to the storage media controller. In addition, another selector 409 can be added in the device, the input terminals of which are respectively connected to the active slave selector 445 and the parallel-to-serial converter 423, and the output terminals are connected to the serial-to-parallel converter 443, according to a Control the signal (Loopback) to select the normal sending and receiving path, or send the serial signal converted by the parallel-to-serial converter 423 to the serial-to-parallel converter 443 to form a loop, so as to test the parallel signal and the parallel signal in the system. Whether the encoding and decoding operations between serial signals are correct.

Furthermore, the tandem ATA split physical layer 40 of the present invention is also provided with a power controller (powercontroller) 401, which can respectively receive the physical layer reset signal (PhyReset) and the multi-level power control signal PartSlum1 from the storage medium controller. and PartSlum2 for integrated power saving control on the power supply, wherein PartSlum1 and PartSlum2 can obtain real power control signals Partial1, Slumber1, Partial2 and Slumber2 through the level detector 411 .

The state of the physical chip can also respond to the storage medium controller according to the transmit ready signal (TxReady) from the transmit phase-locked loop 421 and the receive ready signal (RxLocked) from the receive phase-locked loop 441—the above two signals are converted by the level The device 412 forms a multi-level PHY signal (PhyReady).

Next, please refer to FIG. 3 , which is a circuit block diagram of another embodiment of the present invention. As shown in the figure, its main structure is roughly the same as that of the embodiment shown in FIG. 2 , but a control signal decoder 481 and a status signal encoder 483 can still be added. The control signal decoder 481 is connected to the set of parallel signal transmission lines (TxData[4:0]) to receive a data signal including a valid signal to be transmitted, and can decode the data signal to obtain a valid signal to be transmitted (TxValid ) and then sent to the parallel-to-serial converter respectively, which can reduce the number of pins required for a connection. The status signal encoder 483 is connected to the serial-to-parallel converter 443, and can encode the received quiet signal (SigQuiet) from the selector 403 into the data signal, and then pass through the group of parallel signal receiving lines (RxData[4:0 ]) to the storage media controller, and one connection pin can be reduced.

In addition, the phase-locked loop of the present invention can also be equipped with multiple transmission rate switching options, and can use a signal line (not shown) to connect to the storage media controller, so as to receive control signals from the storage media controller to achieve different transmission rates. The switching action can meet the different transmission rates of different generations of Serial ATA specifications. In addition, the circuit structure of the present invention can be integrated into a separate physical layer chip, which can facilitate production and save costs.

Please refer to FIG. 4 and FIG. 5 , which are respectively timing diagrams of the multi-level power control signal and the multi-level physical layer ready state signal of the present invention. As shown in Figure 4, the storage media controller converts the power control signal through multi-level, and uses a multi-level PartSlum signal to represent the two signals of Partial or Slumber. The low level state (V-low) represents no action on Partial or Slumber; the middle level state (V-mid) represents Partial; the high level state (V-high) represents Slumber. The physical chip obtains the real power control signal through level detection.

As shown in Figure 5, the physical layer ready signal (PhyReady) of the present invention is a multi-level status signal formed by superimposing the transmit ready signal (TxReady) and the receive ready signal (RxLocked), that is, when the transmit phase-locked loop is not yet ready When the physical layer ready signal is in the low level state (V-low); only when the sending phase-locked loop is ready, it is in the middle level state (V-mid); and when both the sending and receiving phase-locked loops are ready, then It is a high level state (V-high).

Also, please refer to FIG. 6 and FIG. 7 , which are schematic diagrams of timing diagrams for decoding the sending valid signal and encoding the receiving static signal, respectively, according to the present invention. Among them, TxData[4:0] and RxData[4:0] are the data signals before decoding and encoding respectively, and TxData-de[4:0] and RxData-en[4:0] are the data signals after decoding respectively. and the encoded data signal, TxValid-de is the decoded transmitted valid signal. Because when converting 8bits data into 10bits signals, it is impossible for normal encoding to generate all data signals that are both 0 or 1, so we can use this feature to send a control signal encoder on the storage media controller side. In the interval where the effective signal is low level, all the data signals to be sent in this interval are replaced by all being 0 or all being 1, and the control signal decoder in the physical chip decodes it to obtain a valid signal for sending. In terms of static signal encoding, the state signal encoder in the physical chip replaces the received data signal in this interval with all 0s or 1s in the interval where the static signal is received at high level, and in the storage media controller The terminal signal decoder obtains the received static signal accordingly.

Utilizing the above-mentioned circuit structure and signal encoding method, the design can be simplified and the function of the separate physical layer can be brought into play most effectively, and the connection pins required for it and the storage medium controller can also be greatly reduced. For the first In terms of the second-generation Serial ATA specification, it can even be reduced to less than 27 pins (the Loop Back pin is used for testing and does not need to be connected to the control module), and can be directly connected to the original storage media bus. No additional control chip pins are needed, which not only greatly reduces the production cost, but also allows system designers to consider whether to use serial ATA and decide whether to add a separate physical layer chip without modifying the motherboard design.

To sum up, it should be known that the present invention relates to a circuit structure of an ATA interface, especially a circuit structure capable of reducing the number of serial ATA separated physical layer interface signals, which mainly utilizes a digital and analog separation structure , making high-frequency analog circuits in separate physical layer chips, and using the characteristics of the interface signal itself and the characteristics of ten-bit data encoding to transmit or encode part of the control and status signals as a multi-level signal in the data signal, It can effectively reduce the interface signal required for connection. Therefore, this invention is actually a novelty, advancement, and an invention that can be used by the industry. It undoubtedly meets the requirements for patent application. I submit an application for an invention patent according to law. I sincerely hope that your review committee will grant this invention patent as soon as possible. I really appreciate it.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the implementation scope of the present invention, that is, any equal changes and changes made according to the shape, structure, characteristics and spirit described in the scope of the patent application of the present invention Modifications should be included in the patent application scope of the present invention.

Claims (3)

1. A signal coding method that can reduce the number of serial ATA split physical layer pins, characterized in that: a state signal encoder and a control signal decoder are set in the serial ATA split physical layer, wherein The state signal encoder is connected to the storage medium controller through a parallel signal receiving line, and the control signal decoder is connected to the storage medium controller through a parallel signal sending line, and the state signal encoder, the control signal decoder and the storage medium controller are transmitted For data signals, the control signal from the storage media controller is encoded in the data signal by the control signal encoder at the storage media controller end, and decoded by the control signal decoder. Status is encoded in the data signal by a status signal encoder, thereby reducing the number of connected pins. 2. The signal encoding method according to claim 1, wherein if the data signal is transmitted from the storage medium controller to the serial ATA separation type physical layer, the control signal encoder at the storage medium controller end can be used in In the falling interval of the sending effective signal, replace all the data with 0 or all 1, and decode it by the control signal decoder. 3. The signal encoding method according to claim 1, wherein if the data signal is transmitted from the serial ATA split physical layer to the storage medium controller, the state signal encoder can rise when receiving the static signal In the interval, replace all the data with 0 or all with 1.

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