CN100353172C - Group delay testing method and device - Google Patents

Abstract

The invention provides a group delay test method for testing group delay T of a tested device_gd. The group delay test method comprises the following steps: inputting an analog single-frequency signal with a known period T to an input end of the tested device; (B) extracting the input single-frequency signal and a delayed single-frequency signal output after passing through the tested device, and respectively converting the input single-frequency signal and the delayed single-frequency signal into a first digital signal and a second digital signal; (C) compare the firstA phase difference of the second digital signal; converting the comparison result of the phase difference into a current I which is in direct proportion to the phase difference; (E) making the obtained current I flow through an average circuit with a known resistance value R, and obtaining a voltage difference delta V; and (F) obtaining the group delay T of the tested device according to the known period T, the current I, the resistance value R and the voltage difference delta V_gd。

Description

Group delay testing method and device

technical field

The invention relates to a group delay testing method and device, in particular to a testing method and device for testing the group delay of the tested device by sending a single frequency signal into the tested device.

Background technique

When a general electronic device circuit transmits a data signal, the delay (that is, the time spent) encountered by the signal passing through the electronic device circuit is called group delay. Group delay has a non-negligible impact on many electronic devices. For example, in data storage systems, if the group delay of internal electronic devices cannot be fully grasped, the relative timing accuracy of data reproduction cannot be guaranteed. This situation will cause Data decoding error. In addition, for a digital communication system, if the group delay is not properly dealt with, it will cause nonlinear distortion of the signal, resulting in an increase in the decoding error rate of the digital signal. Therefore, the measurement of group delay is very important for many electronic devices.

The previous group delay test method is to send a multi-tone source (multi-tone source) into a device under test (DUT), as shown in Figure 1, the multi-tone source contains two high-frequency The signals 11 and 12 (high frequency components) have a slight frequency difference Δf between them, such as high frequency signals with frequencies of 40 MHz and 40.05 MHz respectively. After the two high-frequency signals are sent into and passed through the device under test, the phase difference ΔP between the high-frequency signals 11 and 12 can be obtained through discrete Fourier transform (DFT, Discrete Fourier Transform) calculations. The relevant calculation process must It is calculated by the preset test equipment and program design. Since the group delay T _gd =-Δp/Δf, the group delay can be calculated after calculating Δf and Δp.

In order to test the group delay of the high-frequency band (cut-off band) in the above-mentioned existing group delay test method, the simulated multi-frequency signal source sent into the DUT must be a high-frequency signal, and in order to implement DFT, this simulated multi-frequency signal source must be a high-frequency signal. These high-frequency signals 11 and 12 in the multi-frequency signal source are digitized. Therefore, if the testing equipment used has insufficient sampling data and insufficient resolution, it will be difficult to correctly calculate the phase difference data, resulting in inaccurate test results. As for the existing group delay test method to obtain accurate results, the relevant instruments used must not only have a high-speed digitizer (digitizer) to quickly digitize these high-frequency signals, but also use high-resolution test methods. The equipment cooperates with the program design to detect and calculate the actual value of the phase difference. Since the high-speed digitizer and high-resolution test equipment are very expensive, the overall test cost is very high.

As mentioned above, it can be concluded that the existing group delay testing methods have the following shortcomings:

1 Must use multi-frequency signal source to send to the device under test for group delay test.

2. It is necessary to use a high-speed digitizer to digitize the part of these multi-frequency signals sent by the multi-frequency signal source.

3 High-resolution testing instruments are needed to actually detect and calculate the phase difference value.

4. The aforementioned high-speed digitizers and high-resolution test instruments are very expensive, so they must cost a relatively high cost.

Contents of the invention

Therefore, the object of the present invention is to provide a testing method and device that can significantly reduce the testing cost and accurately obtain the group delay of the device under test.

Therefore, the group delay test method of the present invention is suitable for testing the group delay T _gd of a device under test, and the group delay test method includes the following steps: (A) inputting an analog single-frequency signal with a known period T to the test device (B) extracting the input single-frequency signal and a delayed single-frequency signal output after passing through the device under test, and combining the input single-frequency signal with the delayed single-frequency signal The signals are respectively converted into a first digital signal and a second digital signal; (C) comparing the phase difference between the first and second digital signals; (D) converting the obtained phase difference comparison result into a current proportional to the phase difference I; (E) passing the resulting current I through an averaging circuit of known resistance value R and obtaining a voltage difference ΔV; and (F) based on these known periods T, current I, resistance value R and voltage difference ΔV , to obtain the group delay T _gd of the device under test.

Description of drawings

Other features and advantages of the present invention will be clearly understood in the following detailed description of preferred embodiments with reference to the accompanying drawings. In the accompanying drawings:

Fig. 1 is the timing diagram of two multi-frequency signals of a multi-frequency signal source adopted by the existing group delay testing method;

Fig. 2 is a schematic block diagram of a group of delay testing devices pre-connected to a device under test, for illustrating a preferred embodiment of the group delay testing method of the present invention;

Fig. 3 is a simplified block diagram of the test device in a test state in the preferred embodiment; and

FIG. 4 is a simplified block diagram of the test device in a calibration state in the preferred embodiment.

Detailed ways

Referring to FIG. 2 , it is a schematic diagram of a test device for implementing the above group delay test method according to an embodiment of the present invention. The test device is pre-connected with a device under test 2 for measuring the group delay T _gd of the device under test 2 .

The testing device includes a signal source 31 , a calibration unit 32 , a first conversion circuit 33 , a second conversion circuit 34 , a phase detector 35 , an upper current pump 36 , a lower current pump 37 and an average circuit 38 .

The signal source 31 can output an analog single-frequency signal 311 and supply the single-frequency signal 311 to an input terminal 21 of the device under test 2 . In this embodiment, the single-frequency signal 311 is a sine wave signal with a known period of T. After the single-frequency signal 311 passes through the device under test 2, it is output from an output terminal 22 of the device under test 2 after a delay. Single frequency signal 23.

In this embodiment, the calibration unit 32 adopts a measurement multiplexer (calibrationMultiplexer), which functions as an input switch and can be used in a test state and a calibration state. When in the test state, the device under test The single-frequency signal 311 and the delayed single-frequency signal 23 respectively transmitted by the input terminal 21 and the output terminal 22 of 2, as shown in FIG. 3 , are sent to the first and second conversion circuits 33 respectively through the correction unit 32 , 34 to measure the group delay T _gd of the device under test 2 . When in the calibration state, the single-frequency signal 311 transmitted by the input terminal 21 of the device under test 2 passes through the calibration unit 32 and is sent to the first and second conversion circuits 33 and 34 at the same time, thereby measuring the overall The error value generated by the mismatch of the group delay test device itself. The above-mentioned measurement of the group delay T _gd and the measurement of the error value caused by the mismatch of the overall group delay test device itself will be described in detail below.

The test status will be described first.

The input ends 331, 341 of the first and second conversion circuits 33, 34 are respectively connected to the input ends 21 and 341 of the device under test 2 through the calibration unit 32 in the test state shown in FIG. 3 . The output terminal 22, therefore, can respectively extract the single-frequency signal 311 belonging to the analog signal and the delayed single-frequency signal 23 to be digitized, and then output a first digital signal 333 and a second digital signal 343 respectively by its output terminals 332 and 342, Both the first and second digital signals 333 and 343 obtained by digitizing the sine wave are square wave signals.

The phase detector 35 is used to receive and compare the first and second digital signals 333 and 343 output by the first and second conversion circuits 33 and 34, and output the first and second digital signals by an output terminal 351 thereof Phase difference comparison data between 333 and 343.

The upper and lower current pumps 36, 37 are connected in series, and are controlled by the output terminal 351 of the phase detector 35 at the same time. The phase difference detected by the phase detector 35 is used to control the upper and lower current pumps 36. , 37 internal switches, so that the series connection of the upper and lower current pumps 36, 37 flows out a current I proportional to the phase difference.

The average circuit 38 can adopt a low-pass filter circuit with a known resistance value R. The average circuit 38 is connected to the loop of the current I output by the upper and lower current pumps 36 and 37, and the current I flows through the average circuit. 38 , the information can be converted into a fixed voltage, and a voltage difference ΔV is generated at an output terminal 381 of the averaging circuit 38 .

From the signal flow of the circuit block shown in Figure 3, it can be concluded that its calculation formula is ΔV=(T _gd /T)×I×R, in the period T, current I, resistance value R, and voltage difference ΔV When the equivalent values are known, the group delay T _gd of the device under test 2 can be easily calculated. The above calculation formulas related to the signal flow through the circuit blocks are generally used by ordinary developers when designing circuits, so they will not be deduced in detail here.

Because in the design of this embodiment, the phase difference comparison result output by the phase detector 35 is used to control the upper and lower current pumps 36, 37, and the phase difference is converted into a current I, and then the current I is used to flow through a circuit with a resistance value The average circuit 38 of R generates the voltage difference ΔV, which is a constant value, so it is extremely easy to be accurately measured, and since the actual values of the first and second digital signals 333, 343 do not need to be directly measured during the entire measurement process Therefore, it is not necessary to use expensive high-speed digitizers and high-resolution instruments to accurately measure the actual value of the phase difference as in the existing group delay test method, so that the test device used in the group delay test method of the present invention is not only The device cost can be significantly saved, and the group delay T _gd of the device under test 2 can be obtained effectively and accurately.

The following will continue to describe in detail the calibration state shown in FIG. 4 .

When in the calibration state, the single-frequency signal 311 transmitted by the input terminal 21 of the device under test 2 is repeatedly extracted synchronously by the calibration unit 32, and sent to the first and second conversion circuits 33, 34 respectively. The input terminals 331, 341 are converted synchronously to obtain the first and second digital signals 333, 343 respectively, and then the phase detector 35 will also use the phase difference result obtained by comparing the first and second digital signals 333, 343, To control the upper and lower current pumps 36, 37 to flow a current proportional to the phase difference through the average circuit 38, so as to generate a voltage error value ΔV'. In this calibration state, since the signals input to the first and second conversion circuits 33 and 34 are the same signal, when there is no mismatch in the overall test device, the voltage error value ΔV' will be equal to zero, but if there is a mismatch in the test device , then the voltage error value ΔV' will be a predetermined value, and when actually calculating the group delay T _gd , the voltage error value ΔV' must be taken into account, as for taking the voltage error value ΔV' into consideration , the voltage error value ΔV' must be deducted from the voltage difference ΔV, that is, its calculation formula will be ΔV-ΔV'=(T _gd /T)×I×R, so as to obtain the corrected group delay T _gd .

As mentioned above, since the phase detector 35 is used to compare the digitized signal of the single-frequency signal 311 and the delayed single-frequency 23 in this embodiment, the upper and lower current pumps 36, 37 are controlled by outputting the phase difference result therebetween, The phase difference is converted into a current I, and the current I is used to flow through the averaging circuit 38 with a resistance value R to generate a constant voltage difference ΔV that is easy to measure accurately. Therefore, in the entire measurement process, there is no need to directly measure the first and second voltages. The actual phase difference values of the two digital signals 333, 343 can have the following advantages: (1) only a single-frequency signal source is required to be sent to the device under test for group delay testing; (2) group delay testing device (3) The design of the group delay test device does not need to use expensive high-resolution test instruments to detect the actual value of the calculated phase difference. (4) The test cost can be effectively reduced, and the group delay of the device under test 2 can be accurately obtained. Therefore, the purpose of the invention can indeed be achieved.

The above descriptions are only preferred embodiments of the present invention, but should not limit the implementation scope of the present invention. Various equivalent changes and improvements can be made by those skilled in the art without departing from the spirit and scope of the present invention defined by the appended claims.

Claims (12)

1. group delay method of testing is used for testing the group delay T of a device under test _Gd, this group delay method of testing comprises following steps:

(A) the simulation simple signal of input one known periods T is to an input end of described device under test;

(B) extract this simple signal and a delay back simple signal, and convert this simple signal and this delay back simple signal to one first digital signal and one second digital signal respectively by being exported behind the described device under test;

(C) phase differential of this first, second digital signal relatively;

(D) comparative result of phase differential is converted to an electric current I that is proportional to this phase differential;

(E) make this electric current I averaging circuit of a known value R of flowing through, and obtain a voltage difference delta V; And

(F), try to achieve the group delay T of described device under test according to these known period T, electric current I, resistance value R and voltage difference delta V _Gd

2. group delay method of testing as claimed in claim 1, wherein, this simple signal that described step (A) is imported is a sine wave signal.

3. group delay method of testing as claimed in claim 1, wherein, this first, second digital signal of described step (B) conversion gained is all square-wave signal.

4. group delay method of testing as claimed in claim 1, wherein, described step (D) converts this phase differential comparative result to this electric current I by the Control current pump.

5. group delay method of testing as claimed in claim 4, wherein, the upper and lower current pump that described step (D) is utilized this phase differential to control to be in series, and make this electric current I flow to described averaging circuit by upper and lower current pump serial connection place.

6. group delay method of testing as claimed in claim 1, wherein, the described averaging circuit of described step (E) adopts a low-pass filter circuit.

7. group delay method of testing as claimed in claim 1, wherein, described step (F) is according to a calculating formula Δ V=(T _Gd/ T) * I * R tries to achieve this group delay T _Gd

8. group delay method of testing as claimed in claim 1 also includes step (the A1)～step (A4) between described step (A) and described step (B), wherein:

Described step (A1) synchronously repeats to extract described simple signal, and the described simple signal that will repeat to extract is changed synchronously and obtained first, second digital signal respectively;

The phase differential of first, second digital signal that described step (A2) is relatively obtained in described step (A1);

Described step (A3) will convert an electric current that is proportional to described phase differential at the phase differential comparative result that described step (A2) obtained to;

Described step (A4) makes the electric current of gained in described step (A3) the described averaging circuit of flowing through, and obtains a voltage error value Δ V '; With

Described step (F) is being calculated group delay T _GdThe time, also this voltage error value Δ V ' is taken into account.

9. group delay method of testing as claimed in claim 8, wherein, described step (F) is according to a calculating formula Δ V-Δ V '=(T _Gd/ T) * I * R tries to achieve this group delay T _Gd

10. a group delay proving installation is used for testing the group delay of a device under test, and this proving installation comprises:

One signal source is in order to export the input end of a simple signal of simulating to described device under test;

One first change-over circuit, one input end is connected in the input end of described device under test, gives digitizing in order to the simulating signal that will be extracted;

One second change-over circuit, one input end can be connected in an output terminal of described device under test, give digitizing in order to the simulating signal that will be extracted;

One phase detectors in order to receiving and the digitized signal exported of this first, second change-over circuit relatively, and are exported phase differential comparative result between these digitized signals by the one output terminal;

The upper and lower current pump that is in series in order to being controlled by the output terminal of described phase detectors simultaneously, and flows out an electric current that is proportional to described phase differential by upper and lower current pump serial connection place; And

One averaging circuit is connected on the loop of the electric current that upper and lower current pump exports, and an output terminal that is used to described averaging circuit produces a voltage difference.

11. group delay proving installation as claimed in claim 10, also include the correcting unit that to select to use at a test mode and a correcting state, when in described test mode, after the input end of described device under test and the signal of output terminal are admitted to this correcting unit earlier, be sent to described first, second change-over circuit more respectively; When at described correcting state, the signal of the input end of described device under test is sent to first, second change-over circuit simultaneously by described correcting unit, thereby measures the error amount that the mismatch of whole group delay proving installation own is produced.

12. group delay proving installation as claimed in claim 10, wherein, described averaging circuit is a low-pass filter circuit.

Images