CN114563682B - Method and apparatus for calculating static delay time sequence of integrated circuit - Google Patents

Abstract

The invention relates to a method for calculating static delay time sequence of an integrated circuit by using a test circuit, a computer readable storage medium and a processor, wherein a first voltage is input into the test circuit to obtain a first total delay time; inputting a second voltage to the test circuit to obtain a second total delay time; look-up table to obtain first delay time sequence ratio of logic module under two voltages; look-up table to obtain a second delay timing ratio of the wiring at two voltages; the delay timing of the logic module and the wiring is derived based on the first total delay time, the second total delay time, the first delay timing ratio, and the second delay timing ratio.

Description

Method and device for calculating static delay timing of integrated circuits

Technical field

The present invention relates generally to the field of test circuits. More specifically, the present invention relates to a method for calculating static delay timing of an integrated circuit using a test circuit, a computer-readable storage medium and a processor.

Background technique

With the development of semiconductor technology, the chip manufacturing process has entered the nanometer level. Although the chip has more functions and higher performance, it also greatly increases the circuit complexity, especially the chip's sensitivity to process defects, material defects, and lifespan. Process deviations such as defects and environmental changes such as voltage and temperature are becoming more and more sensitive. Interconnect delay has become one of the issues that urgently need to be solved in static timing analysis of integrated circuits.

The process fluctuations of interconnection mainly come from two aspects. The first aspect is caused by the uneven thickness of the metal and insulating layers produced during the chemical mechanical polishing process during the production process; the second aspect is caused by the interconnection line width and line spacing produced during the pattern making and etching processes. Caused by inconsistencies with design dimensions, this includes two effects: line edge roughness and line width roughness. Interconnect size errors caused by process fluctuations directly change parameters such as interconnect parasitic resistance (R) and capacitance (C), thereby affecting circuit characteristics.

Currently, there is no dedicated test circuit to specifically quantify the actual static delay timing of the chip. Therefore, a solution that uses a test circuit to calculate the static delay timing of the integrated circuit is urgently needed.

Contents of the invention

In order to at least partially solve the technical problems mentioned in the background art, the solution of the present invention provides a method for calculating the static delay timing of an integrated circuit using a test circuit, a computer-readable storage medium, and a processor.

In one aspect, the present invention discloses a method for calculating static delay timing of an integrated circuit using a test circuit. The integrated circuit includes a logic module and wiring, and the test circuit is connected to the logic module and the wiring. The method includes: inputting a first voltage to the test circuit to obtain a first total delay time Td1; inputting a second voltage to the test circuit to obtain a second total delay time Td2; and looking up a table to obtain the logic The first delay timing ratio Rc of the module under the first voltage and the second voltage; look up the table to obtain the second delay timing ratio Rn of the wiring under the first voltage and the second voltage; And based on the first total delay time Td1, the second total delay time Td2, the first delay timing ratio Rc and the second delay timing ratio Rn, derive the delay timing of the logic module and the wiring .

In another aspect, the present invention discloses a computer-readable storage medium on which computer program code for calculating static delay timing of an integrated circuit using a test circuit is stored. When the computer program code is run by a processor, the aforementioned steps are executed. method.

In another aspect, the present invention discloses a processor that uses a test circuit to calculate a static delay timing of an integrated circuit. The integrated circuit includes a logic module and wiring, and the test circuit is connected to the logic module and the wiring. The processor includes: a delay time module, a delay ratio module and a delay timing module. The delay time module is connected to the test circuit, and obtains the first total delay time Td1 based on the first voltage, and obtains the second total delay time Td2 based on the second voltage. The delay ratio module is used to look up the table to obtain the first delay timing ratio Rc of the logic module under the first voltage and the second voltage, and to look up the table to obtain the second delay timing of the wiring under the first voltage and the second voltage. Ratio Rn. The delay timing module is used to derive the delay timing of the logic module and the wiring based on the first total delay time Td1, the second total delay time Td2, the first delay timing ratio Rc and the second delay timing ratio Rn.

The present invention proposes a scheme for calculating the static delay timing of an integrated circuit using a test circuit, specifically quantifying the static delay timing of the integrated circuit, and conducting data comparisons after conducting large-scale tests on actual mass-produced integrated circuits to obtain The static delay timing distribution of the batch integrated circuit is used to guide the physical implementation work and complete more accurate static timing analysis and design for manufacturing (DFM) analysis.

Description of the drawings

The above and other objects, features and advantages of exemplary embodiments of the present invention will become apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the present invention are shown by way of illustration and not limitation, and the same or corresponding reference numerals designate the same or corresponding parts wherein:

Figure 1 is a schematic diagram showing a chip produced by a modern process;

Figure 2 is a circuit diagram showing a 4-to-1 selector;

Figure 3 is a module diagram showing an embodiment of the present invention;

Figure 4 is a logic circuit diagram showing a delayer according to an embodiment of the present invention;

Figure 5 is a logic circuit diagram showing an oscillator according to an embodiment of the present invention;

Figure 6 is a logic circuit diagram showing a counter according to an embodiment of the present invention;

Figure 7 is a waveform diagram showing the counting stage of the embodiment of the present invention;

Figure 8 is a timing relationship diagram showing multiple signals according to an embodiment of the present invention;

Figure 9 is a schematic diagram showing a processor according to an embodiment of the present invention;

Figure 10 is a flow chart illustrating the calculation of static delay timing of an integrated circuit according to an embodiment of the present invention;

Figure 11 is an exemplary connection delay distribution diagram;

Figure 12 shows another exemplary connection delay distribution diagram;

Figure 13 is a diagram illustrating another exemplary connection delay distribution diagram; and

FIG. 14 is a schematic diagram showing a test circuit set according to an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present invention.

It should be understood that the terms “first”, “second”, “third” and “fourth” in the claims, description and drawings of the present invention are used to distinguish different objects, rather than to describe a specific sequence. . The terms "comprising" and "including" used in the description and claims of the present invention indicate the presence of described features, integers, steps, operations, elements and/or components but do not exclude one or more other features, integers , the presence or addition of steps, operations, elements, components and/or collections thereof.

It should also be understood that the terminology used in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification and claims of the present invention, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly dictates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of the present invention refers to and includes any and all possible combinations of one or more of the associated listed items.

As used in this specification and claims, the term "if" may be interpreted as "when" or "once" or "in response to determining" or "in response to detecting" depending on the context.

Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Figure 1 shows a schematic diagram of a chip produced by a modern process. The main core of the chip is an integrated circuit 101 and wires 102. The integrated circuit 101 contains a plurality of circuit elements to implement one or more logical functions. The integrated circuit 101 includes a plurality of pins 103, which serve as input/ The access port for output signal transmission. The wires 102 are used to electrically connect the pins 103 of each integrated circuit 101 so that each integrated circuit 101 cooperates to implement specific logic system functions. The entire logic system also includes an input/output interface 104, which serves as the input/output signal terminal of the logic system. The integrated circuit 101 and the wires 102 are packaged into a chip 105. The chip 105 includes pins 106, which are connected to the input/output interface 104 and transmit the input/output signals of the logic system to the outside of the chip 105.

The integrated circuit 101 can be divided into a base layer and a metal layer. Various library units and standard circuit units are arranged on the base layer, which are collectively called logic modules in the present invention. The metal layer has several stacked metal layers. Wiring, these wires are combined with through holes to electrically connect each logic module, so that signals can be transmitted between each logic module to realize the logic function of the integrated circuit 101. Figure 2 exemplarily shows a circuit diagram of a 4-to-1 selector 200. The selector 200 includes 4 AND gates 201, 2 NOT gates 202, 1 OR gate 203 and multiple wirings 204. The selector signal S ₁ is selected. AND S ₂ controls one of the four input signals w, x, y, z to become the output signal p. Among them, the AND gate 201, the NOT gate 202, the OR gate 203, etc. are logic modules generated on the silicon chip, and the wiring 204 They are the lines that electrically connect each logic module through vias and metal layers.

In practice, the transistors of these logic modules may operate at different voltage thresholds. Common voltage thresholds include ultra low voltage threshold (uLVT), low voltage threshold (low voltagethreshold, LVT), and standard voltage threshold ( standard voltage threshold (SVT) and high voltage threshold (LVT). The lower the voltage threshold the logic module operates at, the lower its dynamic power consumption, but the more serious the leakage will be. There is a logarithmic relationship between leakage and frequency, that is, if the maximum operating frequency increases by 1 time, the leakage will increase by 10 times. Therefore, the operating voltage of integrated circuits does not always pursue low thresholds. Instead, a small number of key logic modules adopt ultra-low voltage thresholds, and the rest adopt low voltage thresholds, standard voltage thresholds, or high voltage thresholds to optimize overall performance. Wafer foundries generally provide various parameter values under these voltage thresholds for chip design companies to use for simulation when designing chips.

These logic modules will produce different RC values when operating at different threshold voltages, and because the wiring is implemented in a three-dimensional multi-layer structure on the silicon chip, each metal layer is electrically connected with the help of through holes, and each metal layer also has Different RC values. With the development of semiconductor technology, the chip manufacturing process has entered the nanometer level, making the distance between the logic module and wiring in Figure 2 smaller and smaller. This not only increases the complexity of circuit design, but also makes integrated circuits more vulnerable to process defects and material defects. , life defects and other process deviations, as well as environmental changes such as voltage and temperature, are becoming more and more sensitive, so that the above-mentioned RC values produce obvious errors, and these errors directly affect the interconnection delay, causing timing chaos, and in severe cases, the integrated circuit will fail. working normally.

The test circuit of the present invention is used to quantify the actual static delay timing. After a large number of tests are implemented, the difference between the actual static delay timing and the simulated static delay timing can be obtained, thereby understanding the degree of process deviation.

The following table exemplarily shows the standard resistance value of each layer of metal and through-holes of Taiwan Semiconductor Manufacturing Co., Ltd. under the standard voltage threshold of the 7-nanometer process, where "Via+i" means connecting the i-th metal layer Through holes with the i+1th metal layer, "M+i" represents the i-th metal layer connection.

Table 1

In order to reduce the influence of through holes on the measurement results, the present invention will increase the wiring resistance value on each metal layer to more than 10 times the through hole resistance value. To this end, the last column in the table shows the required wire length, which The wire length is such that the wiring resistance is large enough to ignore the effect of via resistance. For example, assuming that the timing delay of M7 (the seventh metal layer wiring) is to be measured, the test circuit of the present invention sends the test signal into Via2 through the logic module, and the test signal passes through Via2, Via3, Via4, Via5, and Via6 (collectively (via hole ladder) to M7, and then from Via6, Via5, Via4, Via3, Via2 (through hole ladder) back to the test circuit of the present invention to calculate the timing delay of M7. The present invention requires that the wiring length of M7 should be at least 163.80 microns as listed in this row of Table 1. Under this length, the standard resistance value of M7 is 163.80×21.39=3503.68Ω, and the standard resistance value of the through-hole ladder is 2× (53.55+37.72+12.68+12.68+10.07)=253.40Ω. Since the standard resistance value of M7 wiring is more than 10 times greater than the standard resistance value of the through-hole ladder, the resistance of these through-holes can be directly ignored during actual testing, and the actual timing delay of M7 can be obtained. These required wire lengths can be simulated using a circuit simulation program for integrated circuit performance analysis, such as HSPICE, based on the process parameters provided by the wafer foundry such as Taiwan Semiconductor Manufacturing Co., Ltd.

One embodiment of the present invention is a test circuit that quantifies the static delay timing of specific cells in an integrated circuit. Specific cells can be logic modules at different voltage thresholds as well as layer wiring in metal layers. Figure 3 shows the module diagram of this embodiment. The test circuit includes a delay 301, an oscillator 302, a counter 303 and a processor 304. The delayer 301 is used to generate the oscillation enable signal 306, the scan enable signal 307 and the selection signal 308 according to the enable signal 305, wherein the oscillation enable signal 306 is used to drive the oscillator 302, the scan enable signal 307 and the selection signal 308 Used to drive and control counter 303. The oscillator 302 responds to the oscillation enable signal 306 and generates a test signal 309 within a certain time interval to generate oscillation through the specific unit 310 . The counter 303 first resets in response to the reset signal 312, then responds to the scan enable signal 307 to start or stop counting the number of oscillations of the test signal 309 within the same time interval, and responds to the selection signal 308 and the clock signal 311 to send the measured number of oscillations to the signal 313. The clock signal 311 is output to the processor 304, where the clock signal 311 is used to determine the operating frequency of the counter 303 when outputting the number of oscillations. The processor 304 receives the oscillation number signal 313 and measures the oscillation number to quantify the static delay timing. Each component will be described separately below.

FIG. 4 shows a logic circuit diagram of the delayer 301 of this embodiment. Delay 301 includes input terminal 401, buffer 402, buffer 403, buffer 404, buffer 405, buffer 406, buffer 407, OR gate 408, OR gate 409, NOT gate 410, buffer 411, and an output terminal. 412, output terminal 413 and output terminal 414.

The input terminal 401 of the delayer 301 is connected to the input terminal of the buffer 402, the output terminal of the buffer 402 is connected to the input terminal of the buffer 403 and the input terminal of the OR gate 408, and the output terminal of the buffer 403 is connected to the buffer 404. The input terminal and the input terminal of the OR gate 409, the output terminal of the buffer 404 are connected to the input terminal of the buffer 405 and the input terminal of the buffer 406, the output terminal of the buffer 405 is connected to the input terminal of the buffer 407 and the OR gate 408 The other input terminal of the buffer 406 is connected to the output terminal 413 of the delay device 301, the output terminal of the buffer 407 is connected to the other input terminal of the OR gate 409, and the output terminal of the OR gate 408 is connected to the buffer 411 The input terminal of the OR gate 409 is connected to the input terminal of the NOT gate 410. The output terminal of the NOT gate 410 is connected to the output terminal 414 of the delayer 301. The output terminal of the buffer 411 is connected to the output terminal 412 of the delayer 301. .

The enable signal 305 is input to the delayer 301 from the input terminal 401, the oscillation enable signal 306 is output from the output terminal 413 of the delayer 301, the scan enable signal 307 is output from the output terminal 414 of the delayer 301, and the selection signal 308 is output from the delayer 301. The output terminal 412 of 301 outputs.

Figure 5 shows a logic circuit diagram of the oscillator 302 of this embodiment. The oscillator 302 includes an input terminal 501, a NAND gate 502, and an even number of NOT gates (exemplarily showing 6 NOT gates: NOT gate 503, NOT gate 504, NOT gate 505, NOT gate 506, NOT gate 507, NOT gate 508 ) and output terminal 509.

The input terminal 501 of the oscillator 302 is connected to the input terminal of the NAND gate 502. The output terminal of the NAND gate 502 is connected to the input terminal of the specific unit 310 and the output terminal 509 of the oscillator 302. The output terminal of the specific unit 310 is connected to the NAND gate. The input terminal of gate 503, six NOT gates such as NOT gates 503-508 are connected in series, and the input terminal of NOT gate 508 is connected to the other input terminal of NAND gate 502.

The connection between the NOT gates in the figure is represented by a dotted line because a specific unit 310 is connected in series between the NOT gate and the NOT gate, and between the NOT gate 508 and the NAND gate 502. For the sake of simplicity, the connection method is omitted and not shown. As shown in the figure, a specific unit 310 is connected in series between the NAND gate 502 and the NOT gate 503. The purpose of this arrangement is to make the counting range reasonable. On the one hand, the number is large enough to distinguish slight delay differences, and on the other hand, the number is small enough to avoid setting too many counting units. For example, the wiring of the metal layer to be measured is M4, and it is calculated that 17 specific units 310 are needed to allow the counting range to reflect slight delay differences and avoid setting too many counting units, then the oscillator 302 needs to be connected in series with 16 NOT gates. A specific unit 310 is connected in series between the NAND gates and between the NOT gate 508 and the NAND gate 502. A total of 17 specific units 310 are connected in series. Each specific unit 310 is M4, and the line of M4 of each specific unit 310 The length is 94.73 microns, so the influence of the via ladder can be ignored.

The oscillation enable signal 306 is transmitted from the output terminal 413 of the delayer 301 to the input terminal 501 of the oscillator 302. The NAND gate 502 and the NAND gates 503-508 respond to the oscillation enable signal 306 and input the test signal 309 into a plurality of specific units 310. , and finally introduced into another input terminal of the NAND gate 502 to generate oscillation, and the test signal 309 is output by the output terminal 509 of the oscillator 302 . In order to successfully generate oscillation, the signal level of the output terminal of the NAND gate 502 must be consistent with the signal level of the output terminal of the NOT gate 508 (the last stage NOT gate). Therefore, the number of NOT gates in this embodiment must be an even number.

Figure 6 shows a logic circuit diagram of the counter 303 of this embodiment. The counter 303 includes an input terminal 601, an input terminal 602, an input terminal 603, an input terminal 604, and N series-connected flip-flop units 605. In order to complete counting, the N value is preferably 12. The figure exemplarily shows three flip-flops. Unit 605. Each flip-flop unit 605 includes a D flip-flop 606, a buffer 607, a selector 608, a buffer 609 and an inverter 610, which are connected to each other in the manner shown in the figure. Each flip-flop unit 605 can count binary one-bit values 0 and 1. When N flip-flop units 605 are connected in series, it can count N binary bits, that is, it can count up to 2 ^N times. The counter 303 also includes an input terminal 611 and an output terminal 612. The input terminal 611 is connected to the output terminal 509 of the oscillator 302 for receiving the test signal 309.

The scan enable signal 307 is input from the input terminal 601 of the counter 303, the selection signal 308 is input from the input terminal 602 of the counter 303, the clock signal 311 is input from the input terminal 603 of the counter 303, and the reset signal 312 is input from the input terminal 604 of the counter 303. The oscillation number signal 313 is output from the output terminal 612 of the counter 303 .

When the test circuit wants to start oscillation, referring to Figure 7, first let the reset signal 312 form a square wave at time _t1 . In this embodiment, the square wave signal lasts for at least 200 picoseconds, so that all D flip-flops 606 in the counter 303 The value is reset to 0. Then the enable signal 305 changes from low level to high level at time t ₂ , and is maintained for 1000 nanoseconds. The enable signal 305 has three functions for the test circuit. The first one is to control the loop of the oscillator 302. The second one is to realize the selection of the counter 303 clock. The third one is to use the clock signal 311 to start driving the counter 303 to output counting at time t ₃ after the enable signal 305 changes from high level to low level. value. The operation of each component will be described in more detail below.

At time t ₂ , the enable signal 305 changes from low level to high level, and one of the paths of the delay 301 (buffer 402, OR gate 408, buffer 411, output terminal 412) will respond fastest, so The selection signal 308 first changes from low level to high level. The selection signal 308 is input to the input terminal 602 of the counter 303 to control the signal of the clock terminal of each flip-flop unit 605 from the test signal 309 or the clock signal 311. When the selection signal 308 is high level, the selector 608 of this embodiment selects the test signal 309 from the input terminal 611 and transmits the test signal 309 to the clock terminal of the D flip-flop 606 to prepare to start calculating the ring oscillation of the oscillator 302 frequency.

After the selection signal 308 turns to high level, the other path of the delayer 301 (buffer 402, buffer 403, OR gate 409, NOT gate 410, output terminal 414) subsequently responds, so the scan enable signal 307 changes from high level to high level. level changes to low level, the scan enable signal 307 is input to the input terminal 601 of the counter 303, and is transmitted to the SE port of each D flip-flop 606. When the scan enable signal 307 is low level, each D flip-flop The data of the counter 606 arrives from the D port to the Q port, and the counter 303 is ready at this time.

Another path of delayer 301 (buffer 402, buffer 403, buffer 404, buffer 406, output terminal 413) passes through the 4-level buffering of buffer 402, buffer 403, buffer 404, buffer 406, and finally In response, the oscillation enable signal 306 changes from low level to high level, and the oscillation enable signal 306 is input to the input terminal 501 of the oscillator 302 . When the oscillation enable signal 306 is still low level, the output terminal of the NAND gate 502 is high level. When the oscillation enable signal 306 changes from low level to high level, the output terminal of the NAND gate 502 becomes low level. After the low-level test signal 309 passes through multiple specific units 310 (which will not change its level) and six NOT gates 503-508, the output of the NOT gate 508 is low level, so that the output of the NAND gate 502 terminal becomes high level, and after the high-level test signal 309 passes through multiple specific units 310 and six NOT gates 503-508, the output terminal of the NOT gate 508 becomes high level, and the output terminal of the NAND gate 502 becomes low level. Accordingly, while the oscillation enable signal 306 maintains a high level, the test signal 309 oscillates high and low in the oscillation ring.

The test signal 309 is input to the clock terminal of the D flip-flop 606. As the clock signal of the D flip-flop 606, an inverted level signal is formed at the D terminal and the Q terminal based on the NOT gate 610 and the buffer 609. When the voltage of the test signal 309 The level changes by one cycle, and the level of Q terminal changes accordingly. The output terminal of the NOT gate 610 of the previous stage D flip-flop 606 is connected to the input of the selector 608 of the next stage flip-flop unit 605, so that the N flip-flop units 605 start counting according to the high and low oscillation of the test signal 309.

As can be seen from the above, the delayer 301 sequentially drives the selection signal 308, the scan enable signal 307 and the oscillation enable signal 306 to change levels to drive the oscillator 302 to generate an oscillating test signal 309. The counter 303 generates an oscillation signal based on the oscillation of the test signal 309. count.

Since the delay time of the test signal 309 passing through the specific unit 310 is proportional to its RC value, when the actual resistance value of the specific unit 310 is larger than the standard resistance value, the delay time is longer, and vice versa. Therefore, the test circuit of this embodiment measures the number of oscillations of the test signal 309 in unit time (1000 nanoseconds). If the number is high, it means that the delay time of the specific unit 310 is short, that is, the actual resistance value of the specific unit 310 is small. If the number is low, , indicating that the delay time of the specific unit 310 is long, that is, the actual resistance value of the specific unit 310 is large. By detecting the number of oscillations, the difference between the actual static timing delay of a specific unit 310 and the standard static timing delay can be estimated.

After the enable signal 305 maintains a high level for 1000 nanoseconds, the enable signal 305 changes from high level to low level. At this stage, the oscillation enable signal 306 is first caused to change from high level to low level. The oscillation enable signal 306 is at a low level, and the output end of the NAND gate 502 of the oscillator 302 will remain at a high level and will no longer oscillate, thus stopping the ring oscillation operation.

Then the selection signal 308 changes from high level to low level after the 4-level buffer (buffer 402, buffer 403, buffer 404, buffer 405), which controls the selector 608 of the flip-flop unit 605 of the counter 303 Selecting the clock signal 311, the D flip-flop 606 starts operating based on the clock signal 311, which in this embodiment has a period greater than 20 nanoseconds, instead of the test signal 309.

Finally, the scan enable signal 307 changes from low level to high level after five levels of buffering (buffer 402, buffer 403, buffer 404, buffer 405, buffer 407). At this time, the D flip-flop 606 The SE terminal is at a high level, causing the data of the D flip-flop 606 to arrive at the Q port from the SI terminal instead of the D terminal, preparing to perform serial output of counting.

Since the output of the previous stage flip-flop unit 605 of the counter 303 is connected to the SI terminal of the subsequent stage flip-flop unit 605, based on the timing of the clock signal 311, the output terminal 612 of the counter 303 will sequentially start from the last stage flip-flop unit 605. The Q values of each level are forwarded to the processor 304. In other words, the processor 304 first receives the highest binary digit value, then the next highest digit value, until the lowest digit value. Accordingly, the processor 304 obtains a binary oscillation number value.

To sum up, when the enable signal 305 changes from high level to low level, the delayer 301 sequentially drives the oscillation enable signal 306, the selection signal 308 and the scan enable signal 307 to change levels, so that the counter 303 outputs oscillation times to processor 304.

Figure 8 shows the timing relationship diagram of the enable signal 305, the oscillation enable signal 306, the scan enable signal 307 and the selection signal 308. Based on the logic planning of the delayer 301 in this embodiment, the selection signal 308 will be smaller when starting the oscillation. The enable signal 305 is delayed in changing the level, the scan enable signal 307 is delayed in changing the level than the enable signal 305, the oscillation enable signal 306 is delayed in changing the level than the enable signal 305, and the oscillation enable signal 306 is output during counting. The level will change later than the enable signal 305 , the selection signal 308 will change the level later than the oscillation enable signal 306 , and the scan enable signal 307 will change the level later than the selection signal 308 .

In this embodiment, by setting the delayer 301, only one enable signal 305 can be used to generate the oscillation enable signal 306, the scan enable signal 307 and the selection signal 308. As can be seen from Figure 7, this embodiment only needs to provide the enable signal 306. , clock signal 311 and reset signal 312, the test result (oscillation number signal) can be obtained, making the control of the test circuit simpler.

When using the test circuit of this embodiment to actually test a specific unit of the integrated circuit, the specific unit needs to work under two voltages respectively, so that the processor 304 can obtain enough information to calculate the timing delay. Figure 9 shows a schematic diagram of the processor 304 of this embodiment. The processor 304 includes an input terminal 901, a delay time module 902, a delay ratio module 903, a delay sequence module 904 and an output terminal 905. Each module executes the process shown in Figure 10.

Because the wiring is too delicate, it cannot be connected to the test circuit alone for testing. It is necessary to connect the logic module to first obtain the timing delay information of the logic module, and then calculate the timing delay information of the wiring.

In step 1001, a first voltage is input to the test circuit to obtain a first total delay time Td1. The first voltage can be any voltage value acceptable to the integrated circuit, such as 0.75V. The oscillator 302 generates a test signal 309 within a time interval. The test signal 309 is delayed by the time of the logic module and wiring. The counter 303 records the first binary oscillation number and outputs it to the processor 304. The delay time module 902 receives the first number of oscillations through the input terminal 901, and further obtains the first total delay time Td1.

In more detail, the delay time module 902 receives the bit values of the first oscillation number sequentially from the highest bit to the lowest bit of the binary system. For example, the delay time module 902 receives [1 1 1 1 1 0 1 0 0 0 0], which means The number of first oscillations within the time interval is 2000 times. Then the delay time module 902 divides the time interval by the first number of oscillations and then by the number of ring oscillations to obtain the first total delay time Td1, that is:

Td1=time interval/number of first oscillations/number of ring oscillations

The number of ring oscillation stages is the total number of all logic gates in the oscillator 302, that is, the number of specific units 310 connected in series. In this embodiment, it is the total number of NAND gates 502 and NOT gates 503-508, which is 7. Taking the time interval as 1000 nanoseconds, the first oscillation number as 2000 times, and the ring oscillation level as 7 as an example, the first total delay time Td1=1000 nanoseconds/2000/7=71 picoseconds. The first total delay time Td1 reflects the total delay time of a particular unit 310 (logic module plus wiring) when the integrated circuit operates at 0.75V.

In step 1002, a second voltage is input to the test circuit to obtain a second total delay time Td2. The second voltage is also any voltage value acceptable to the integrated circuit, but must be different from the first voltage, such as 0.8V. The oscillator 302 generates a test signal 309 in the same time interval. The test signal 309 is delayed by the time of the logic module and wiring. The counter 303 records the second binary oscillation number and outputs it to the processor 304 . The delay time module 902 receives the bit values of the second oscillation number sequentially from the highest bit to the lowest bit through the input terminal 901. For example, the delay time module 902 receives [1 1 1 1 1 10 1 1 1 0], which means that it is within the time interval. The second number of oscillations is 2030 times. Then the delay time module 902 divides the time interval by the second number of oscillations and then by the number of ring oscillations to obtain the second total delay time Td2. Taking the above example as an example, Td2=1000 nanoseconds/2030/7=70 picoseconds. The second total delay time Td2 reflects the total delay time of the specific unit 310 (logic module, wiring) when the integrated circuit operates at 0.8V.

In step 1003, look up the table to obtain the first delay timing ratio Rc of the logic module under the first voltage and the second voltage. As mentioned before, the wafer foundry will provide various parameter values under the aforementioned voltage threshold. Based on these parameter values, the simulation timing delay shown in Table 2 can be made (based on room temperature 25 degrees Celsius, ultra-low voltage threshold for example).

Table 2

The delay ratio module 903 obtains the first delay timing ratio Rc of the logic module under the first voltage and the second voltage by looking up table 2. The calculation method of the first delay timing ratio Rc is:

Among them, Tc1 is the time delay of the logic module at the first voltage, and Tc2 is the time delay of the logic module at the second voltage. For example, the specific unit to be tested is M3, then:

In step 1004, a table is looked up to obtain the second delay timing ratio Rn of the wiring under the first voltage and the second voltage. The delay ratio module 903 continues to obtain the second delay timing ratio Rn of the wiring under the first voltage and the second voltage through the lookup table 2. The calculation method of the second delay timing ratio Rn is:

Among them, Tn1 is the time delay of the wiring at the first voltage, and Tn2 is the time delay of the wiring at the second voltage. For example, the specific unit to be tested is M3, then:

In step 1005, the delay timing of the logic module and the wiring is derived based on the first total delay time Td1, the second total delay time Td2, the first delay timing ratio Rc, and the second delay timing ratio Rn. The delay timing module 904 derives the timing delay of the logic module and wiring based on the previously obtained first total delay time Td1, second total delay time Td2, first delay timing ratio Rc, and second delay timing ratio Rn, that is:

According to the above formula, the delay sequence module 904 obtains the actual time delay Tc1 of the logic module at the first voltage, the actual time delay Tc2 of the logic module at the second voltage, the actual time delay Tn1 of the wiring at the first voltage, and the actual time delay Tn1 of the wiring at the second voltage. The actual time delay is Tn2. These data are output via the output terminal 905 for subsequent processing.

Through the foregoing method, the test circuit of this embodiment can obtain the timing delay of the logic module and the wiring of the specific metal layer at a specific voltage. In one application scenario, this embodiment is used to test a large number of chips to obtain big data on the process angle connection delay of each layer of metal at a specific temperature. Since each chip has some slight errors in the manufacturing process, based on these large data Data can be used to determine the process deviation of this batch of chip metal lines. Figure 11 shows an exemplary wiring delay distribution diagram. The dotted line 1101 indicates that the wiring is 20% faster than the standard deviation in the simulation environment. The dotted line 1102 indicates that the wiring is 20% slower than the standard process deviation in the simulation environment. The columnar The picture is the actual measured distribution. It can be seen that the data is normally distributed near 0%, indicating that there is no deviation in the RC value of the wiring of this batch of chips. Figure 12 shows another exemplary wiring delay distribution diagram, showing that the RC value of the wiring of this batch of chips is larger than that of the standard process, so that the overall timing delay is slower. Figure 13 shows another exemplary wiring delay distribution diagram, showing that the RC value of the wiring of this batch of chips is smaller than that of the standard process, so that the overall timing delay is faster.

This embodiment proposes a test circuit to specifically quantify the timing delay of the chip's logic module and metal layer wiring, and compares the data after a large number of tests on the actually produced chips to obtain the overall timing delay distribution of the chip. This guides the work of physical implementation.

Another embodiment of the present invention is a test circuit group composed of the test circuit framework of FIG. 3 to test multiple specific units at one time. FIG. 14 shows the test circuit set of this embodiment. The test circuit set includes a delayer 1401, a multi-stage test circuit 1402 and a processor 1403.

The delayer 1401 has the same function as the delayer 301, and is used to generate an oscillation enable signal, a scan enable signal and a selection signal according to the enable signal. Each stage of the test circuit 1402 includes an oscillator 1404 and a counter 1405. The oscillator 1404 has the same function as the oscillator 302. It responds to the oscillation enable signal and generates test signals within a time interval to generate oscillation through multiple specific units 1406. The function of the counter 1405 The same as the counter 303, it first responds to the reset signal to reset, then receives the test signal that generates oscillation, then responds to the scan enable signal to start or stop counting the number of oscillations of the test signal within the same time interval, and responds to the selection signal and clock signal to measure the number of oscillations. The obtained oscillation number signal is output. The processor 1403 has the same function as the processor 304, receiving the oscillation number signal and measuring the oscillation number to quantify the static delay timing.

If the chip to be tested has N specific units, this embodiment can configure N-level test circuits 1402, with each level of test circuit 1402 testing one specific unit 1406. The counter 1405 of each stage test circuit 1402 is connected in series with the counters 1405 of the upper and lower stage test circuits 1402, and the output end of the counter 1405 of the last stage test circuit 1402 is connected to the processor 1403.

For example, if the specific unit to be tested has a logic module under an ultra-low voltage threshold, a logic module under a low voltage threshold, a logic module under a standard voltage threshold, and a total of 13 connections from M2 to M11, then this embodiment The test circuit group needs to be configured with a 13-level test circuit 1402, that is, N is 13. Each level is connected to a specific unit 1406, for example, specific unit 1 is M11, specific unit 2 is M10, specific unit 3 is M9, specific unit 4 is M8, specific unit 5 is M7, specific unit 6 is M6, and specific unit 7 is M5. , the specific unit 8 is M4, the specific unit 9 is M3, the specific unit 10 is M2, the specific unit 11 is a logic module under the standard voltage threshold, the specific unit 12 is a logic module under the low voltage threshold, and the specific unit 13 is ultra-low voltage. Logic modules under threshold.

When the test circuit group wants to start oscillation, first let the reset signal reset all D flip-flops in the counter 1405, then the enable signal changes from low level to high level, and the delayer 1401 controls the selection signal to change from low level to high level at the earliest. A high level causes the test signal to be transmitted to the clock terminal of the D flip-flop in the counter 1405. The delayer 1401 then controls the scan enable signal to change from high level to low level, so that the data of each D flip-flop in the counter 1405 reaches the Q port from the D port. At this time, the counter 1405 is ready. The delayer 1401 finally controls the oscillation enable signal to change from low level to high level and input it to each oscillator 1404. The test signal starts to oscillate high and low in the oscillation ring, and the counter 1405 counts according to the oscillation of the test signal.

After the enable signal maintains a high level for a period of time, the enable signal turns to a low level, and the delayer 1401 first controls the oscillation enable signal to turn from a high level to a low level, so that the oscillator 1404 stops oscillating. Then the delayer 1401 controls the selection signal to change from high level to low level, and the D flip-flop of the counter 1405 starts to work according to the clock signal instead of the test signal. Finally, the delayer 1401 controls the scan enable signal to change from low level to high level and starts to serially output the count data.

As shown in Figure 14, a counter 1405 that counts the number of oscillations of a specific unit N is directly connected to the processor 1403, followed by a counter 1405 that counts the number of oscillations of a specific unit N-1, and then a counter 1405 that counts the number of oscillations of a specific unit N-2. Until the counter 1405 at the end counts the number of oscillations of specific unit 1, so the processor 1403 first receives the number of oscillations of specific unit N, then counts the number of oscillations of specific unit N-1, and then counts the number of oscillations of specific unit N-2. , and finally counts the number of oscillations of specific unit 1.

Taking the above-mentioned 13 specific units to be tested as an example, the processor 1403 will receive the oscillation number signal of each specific unit 1406 in the following order: logic module under ultra-low voltage threshold, logic module under low voltage threshold, standard voltage threshold The following logic modules, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11.

After receiving the oscillation times of all specific units 1406, the processor 1403 executes the process shown in Figure 10 to obtain the timing delays of each specific unit 1406 at two operating voltages. This embodiment can be further used to test a large number of chips. to obtain the connection delay distribution of each specific unit 1406 of the batch of chips.

This embodiment proposes a test circuit set that simultaneously quantifies the timing delays of all or part of the logic modules and metal layer wiring of the chip, and compares the data after a large number of tests on the actually produced chips to obtain the chip's Overall timing delay distribution to guide the physical implementation work.

Another embodiment of the present invention is a computer-readable storage medium on which is stored a computer program code for calculating a static delay sequence of an integrated circuit using a test circuit. When the computer program code is run by a processor, the execution is as shown in Fig. The method described in 10.

The present invention specifically quantifies the static delay timing of the integrated circuit to obtain the static delay timing distribution of the integrated circuit, thereby guiding the work of physical implementation and completing more accurate static timing analysis and manufacturability design analysis, and more accurate Static timing analysis and design-for-manufacturability analysis help back-end implementations adopt higher operating frequencies while taking yield into account.

It should be noted that, for the purpose of simplicity, the present invention describes some methods and their embodiments as a series of actions and their combinations, but those skilled in the art can understand that the solution of the present invention is not limited by the sequence of the described actions. . Therefore, based on the disclosure or teaching of the present invention, those skilled in the art can understand that certain steps may be performed in other orders or simultaneously. Furthermore, those skilled in the art can understand that the embodiments described in the present invention can be regarded as optional embodiments, that is, the actions or modules involved are not necessarily necessary for the implementation of one or some solutions of the present invention. In addition, according to different solutions, the description of some embodiments of the present invention also has different emphasis. In view of this, those skilled in the art can understand the parts that are not described in detail in a certain embodiment of the present invention, and can also refer to the relevant descriptions of other embodiments.

In terms of specific implementation, based on the disclosure and teachings of the present invention, those skilled in the art can understand that several embodiments disclosed in the present invention can also be implemented in other ways not disclosed herein. For example, as for each unit in the electronic equipment or device embodiment described above, this article splits them based on the logical function, but there may be other splitting methods in actual implementation. As another example, multiple units or components may be combined or integrated into another system, or some features or functions in units or components may be selectively disabled. In terms of connection relationships between different units or components, the connections discussed above in connection with the drawings may be direct or indirect couplings between the units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection using an interface, where the communication interface may support electrical, optical, acoustic, magnetic or other forms of signal transmission.

In the present invention, units described as separate components may or may not be physically separated, and components shown as units may or may not be physical units. The aforementioned components or units may be co-located or distributed over multiple network units. In addition, according to actual needs, some or all of the units may be selected to achieve the purpose of the solutions described in the embodiments of the present invention. In addition, in some scenarios, multiple units in the embodiment of the present invention may be integrated into one unit or each unit may exist physically separately.

The foregoing can be better understood in accordance with the following terms:

Clause A1. A test circuit for quantifying the static delay timing of a specific unit in an integrated circuit, including: an oscillator that responds to an oscillation enable signal to generate a test signal to generate oscillation through the specific unit; a counter that counts within a time interval the number of oscillations; and a processor to quantize the static delay timing according to the number of oscillations.

Clause A2. The test circuit according to Clause A1, wherein the specific unit is one of a logic module and a wiring.

Clause A3. The test circuit according to Clause A2, wherein the logic module adopts one of an ultra-low voltage threshold, a low voltage threshold and a standard voltage threshold.

Clause A4. The test circuit according to Clause A1, wherein the oscillator includes: a NAND gate to input the test signal to the specific unit in response to the oscillation enable signal; and a plurality of series NOT gates to The output signal from the specific unit is input to the NAND gate.

Clause A5. The test circuit according to Clause A4, wherein the counter receives the test signal and starts or stops counting in response to the scan enable signal.

Clause A6. The test circuit according to Clause A5, wherein the counter includes N flip-flop units in series for counting up to 2 ^N times.

Clause A7. The test circuit according to clause A6, wherein the test circuit includes a delayer for generating the oscillation enable signal, the scan enable signal and the selection signal according to the enable signal.

Clause A8. The test circuit according to Clause A7, wherein when the enable signal changes from low level to high level, the delayer sequentially drives the selection signal, the scan enable signal and the The oscillation enable signal changes from low level to high level, and the counter starts counting; when the enable signal changes from high level to low level, the delayer sequentially drives the oscillation enable signal, The selection signal and the scan enable signal change from high level to low level, and the counter outputs the number of times to the processor.

Clause A9. The test circuit according to Clause A7, wherein the selection signal is used to control clock selection of one of the N series flip-flop units from the test signal or the clock signal.

Clause A10. The test circuit according to clause A2, wherein the processor includes: a delay time module to obtain a first total delay time based on the first voltage, and a second total delay time based on the second voltage; a delay ratio module, Use the oscillator to test the logic module to obtain the first delay timing ratio Rc of the logic module under the first voltage and the second voltage, and use the oscillator to test the logic module. The wiring is tested to obtain a second delay timing ratio of the wiring under the first voltage and the second voltage; and a delay timing module is used to determine based on the first total delay time, the second The total delay time, the first delay timing ratio and the second delay timing ratio are used to derive the static delay timing of the logic module and the wiring.

Clause A11. The test circuit according to clause A10, wherein the delay time module is used to: use the counter to calculate the number of first oscillations in the time interval; and divide the time interval by the first oscillation The number of times is divided by the number of ring oscillation stages to obtain the first total delay time.

Clause A12. The test circuit according to Clause A10, wherein the delay time module is used to: use the counter to calculate the number of second oscillations in the time interval; and divide the time interval by the second oscillation The number of times is divided by the number of ring oscillation stages to obtain the second total delay time.

Clause A13. The test circuit according to Clause A11 or 12, wherein the oscillator includes a NAND gate and a plurality of series NOT gates, and the ring oscillation series is the NAND gate and the plurality of series NOT gates. total quantity.

Clause A14. A test circuit set for quantifying the static delay timing of multiple specific units in an integrated circuit, including: a multi-stage test circuit, each stage of the test circuit including: an oscillator, responding to an oscillation enable signal to generate a test signal through the said A specific unit generates oscillation; a counter is used to count the number of times of the oscillation within a time interval; and a processor is used to quantify the static delay timing according to the number of times; wherein the counter is connected in series with a counter of an upper-level test circuit.

Clause A15. The test circuit set according to Clause A14, wherein the plurality of specific units include logic modules and wiring, and the oscillator of each stage of the test circuit is connected to a different specific unit.

Clause A16. The test circuit set according to Clause A15, wherein the logic module adopts one of an ultra-low voltage threshold, a low voltage threshold and a standard voltage threshold.

Clause A17. The test circuit set according to Clause A14, wherein the oscillator includes: a NAND gate responsive to the oscillation enable signal to input the test signal to the specific unit; and a plurality of series NOT gates, The output signal from the specific cell is input to the NAND gate.

Clause A18. The test circuit set according to Clause A17, wherein the counter receives the test signal and starts or stops counting in response to the scan enable signal.

Clause A19. The test circuit set according to clause A18, wherein the counter includes N flip-flop units in series for counting up to 2 ^N times.

Clause A20. The test circuit set according to Clause A19, wherein the test circuit set includes a delayer for generating the oscillation enable signal, the scan enable signal and the selection signal according to the enable signal.

Clause A21. The test circuit set according to Clause A20, wherein when the enable signal changes from low level to high level, the delayer sequentially drives the selection signal, the scan enable signal and all The oscillation enable signal changes from low level to high level, and the counter starts counting; when the enable signal changes from high level to low level, the delayer sequentially drives the oscillation enable signal , the selection signal and the scan enable signal change from high level to low level, and the multi-level test circuit outputs the number of times to the processor.

Clause A22. The test circuit set according to Clause A20, wherein the selection signal is used to control the clock selection of one of the N series flip-flop units from the output of the test signal and the counter of the upper-level test circuit. one of the signals or the clock signal.

Clause A23. The test circuit set according to Clause A15, wherein the processor includes: a delay time module to obtain a first total delay time based on the first voltage, and a second total delay time based on the second voltage; a delay ratio module , used to use the oscillator to test the logic module to obtain the first delay timing ratio Rc of the logic module under the first voltage and the second voltage, and use the oscillator to test the logic module. The wiring is tested to obtain a second delay timing ratio of the wiring under the first voltage and the second voltage; and a delay timing module is used to determine based on the first total delay time, the third The static delay timing of the logic module and the wiring is derived from the two total delay times, the first delay timing ratio and the second delay timing ratio.

Clause A24. The test circuit set according to Clause A23, wherein the delay time module is used to: use the counter to calculate the first number of oscillations in the time interval; and divide the time interval by the first The number of oscillations is divided by the number of ring oscillation stages to obtain the first total delay time.

Clause A25. The test circuit set according to Clause A23, wherein the delay time module is used to: use the counter to calculate the second number of oscillations in the time interval; and divide the time interval by the second The number of oscillations is divided by the number of ring oscillation stages to obtain the second total delay time.

Clause A26. The test circuit set according to Clause A24 or 25, wherein the oscillator includes a NAND gate and a plurality of series NOT gates, and the ring oscillation series is the NAND gate and the plurality of series NOT gates. Total number of doors.

Clause A27. The test circuit set according to clause A14, wherein the processor is connected to the counter of the last stage of the test circuit.

Clause B1. A method for calculating the static delay timing of an integrated circuit using a test circuit. The integrated circuit includes a logic module and wiring. The test circuit is connected to the logic module and the wiring. The method includes: inputting a third Apply a voltage to the test circuit to obtain the first total delay time Td1; input a second voltage to the test circuit to obtain the second total delay time Td2; look up the table to obtain the logic module's response to the first voltage and the first delay timing ratio Rc under the second voltage; look up a table to obtain the second delay timing ratio Rn of the wiring under the first voltage and the second voltage; and based on the first total The delay time Td1, the second total delay time Td2, the first delay timing ratio Rc and the second delay timing ratio Rn are used to derive the delay timing of the logic module and the wiring.

Clause B2. The method according to Clause B1, wherein the step of inputting the first voltage to the test circuit includes: using the test circuit to calculate the first number of oscillations within a time interval; and dividing the time interval by the The first number of oscillations is divided by the number of ring oscillation stages to obtain the first total delay time Td1.

Clause B3. The method according to Clause B1, wherein the step of inputting the second voltage to the test circuit includes: using the test circuit to calculate the second number of oscillations within a time interval; and dividing the time interval by the The second number of oscillations is divided by the number of ring oscillation stages to obtain the second total delay time Td2.

Clause B4. The method according to clause B2 or 3, wherein the test circuit includes an oscillator, the oscillator includes a NAND gate and a plurality of NOT gates, and the ring oscillation series is the NAND gate and all Describe the total number of multiple NOT gates.

Clause B5. The method according to Clause B1, wherein the first delay timing ratio Rc and the second delay timing ratio Rn are obtained by looking up a table.

Clause B6. The method according to Clause B1, wherein the delay timing Tn1 of the wiring at the first voltage is obtained by the following formula:

Clause B7. The method according to Clause B1, wherein the delay timing Tn2 of the wiring under the second voltage is obtained by the following formula:

Clause B8. The method according to Clause B1, wherein the delay timing Tc1 of the logic module under the first voltage is obtained by the following formula:

Clause B9. The method according to Clause B1, wherein the delay timing Tc2 of the logic module under the second voltage is obtained by the following formula:

Clause B10. A computer-readable storage medium on which is stored computer program code for calculating the static delay timing of an integrated circuit using a test circuit. When the computer program code is run by a processor, any one of clauses B1 to 9 is executed. the method described.

Clause B11. A processor that uses a test circuit to calculate the static delay timing of an integrated circuit. The integrated circuit includes a logic module and wiring. The test circuit is connected to the logic module and the wiring. The processor includes: Delay time module, connected to the test circuit, obtains the first total delay time Td1 based on the first voltage, and obtains the second total delay time Td2 based on the second voltage; delay ratio module, used to look up the table to obtain the logic module a first delay timing ratio Rc under the first voltage and the second voltage, and a lookup table to obtain a second delay timing ratio Rn of the wiring under the first voltage and the second voltage ; and a delay timing module for deriving the logic module based on the first total delay time Td1, the second total delay time Td2, the first delay timing ratio Rc and the second delay timing ratio Rn and the delay timing of the wiring.

The embodiments of the present invention have been introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation modes of the present invention. The description of the above embodiments is only used to help understand the method and the core idea of the present invention; at the same time, for Those of ordinary skill in the art will make changes in the specific implementation and application scope based on the ideas of the present invention. In summary, the contents of this description should not be understood as limiting the present invention.

Claims (11)

1. A method for calculating the static delay timing of an integrated circuit using a test circuit, the integrated circuit includes a logic module and wiring, the test circuit is connected to the logic module and the wiring, the method includes: Input the first voltage to the test circuit to obtain the first total delay time Td1; Input the second voltage to the test circuit to obtain the second total delay time Td2; Look up a table to obtain the first delay timing ratio Rc of the logic module under the first voltage and the second voltage; Look up a table to obtain the second delay timing ratio Rn of the wiring under the first voltage and the second voltage; and Based on the first total delay time Td1, the second total delay time Td2, the first delay timing ratio Rc and the second delay timing ratio Rn, derive the delay timing of the logic module and the wiring; in, The first voltage is different from the second voltage. 2. The method of claim 1, wherein the step of inputting a first voltage to the test circuit includes: Using the test circuit to calculate the first number of oscillations within a time interval; and The time interval is divided by the first number of oscillations and then by the number of ring oscillation stages to obtain the first total delay time Td1. 3. The method of claim 1, wherein inputting a second voltage to the test circuit includes: Using the test circuit to calculate the second number of oscillations within the time interval; and The time interval is divided by the second number of oscillations and then by the number of ring oscillations to obtain the second total delay time Td2. 4. The method according to claim 2 or 3, wherein the test circuit includes an oscillator, the oscillator includes a NAND gate and a plurality of NOT gates, and the ring oscillation series is the NAND gate and all Describe the total number of multiple NOT gates. 5. The method of claim 1, wherein the first delay timing ratio Rc and the second delay timing ratio Rn are obtained by looking up a table. 6. The method of claim 1, wherein the delay timing Tn1 of the wiring at the first voltage is obtained by the following formula: 7. The method according to claim 1, wherein the delay timing Tn2 of the wiring under the second voltage is obtained by the following formula: 8. The method of claim 1, wherein the delay timing Tc1 of the logic module under the first voltage is obtained by the following formula: 9. The method according to claim 1, wherein the delay timing Tc2 of the logic module under the second voltage is obtained by the following formula: 10. A computer-readable storage medium on which is stored a computer program code for calculating a static delay sequence of an integrated circuit using a test circuit. When the computer program code is run by a processor, any one of claims 1 to 9 is executed. the method described. 11. A processor that uses a test circuit to calculate the static delay timing of an integrated circuit. The integrated circuit includes a logic module and wiring. The test circuit is connected to the logic module and the wiring. The processor includes: A delay time module, connected to the test circuit, obtains the first total delay time Td1 based on the first voltage, and obtains the second total delay time Td2 based on the second voltage; A delay ratio module, used to look up a table to obtain the first delay timing ratio Rc of the logic module under the first voltage and the second voltage, and to look up the table to obtain the first delay sequence ratio Rc of the wiring under the first voltage. and the second delay timing ratio Rn at the second voltage; and A delay timing module for deriving the logic module and the delay sequence based on the first total delay time Td1, the second total delay time Td2, the first delay timing ratio Rc and the second delay timing ratio Rn. The delay sequence of the above-mentioned wiring; among them, The first voltage is different from the second voltage.