CN100336048C - Data transmission specification determination method and bridge chipset and memory matching device - Google Patents

Abstract

The present invention relates to a method for determining a data transmission specification and a bridge chipset and memory matching device used thereon, which are applied to a central processing unit, a bridge chipset, a bus connecting the two, and a read-only memory electrically connected to the bridge chipset in a computer system. The method includes the following steps: causing the computer system to enter a system coordination state; causing the bridge chipset to read a first specification data representing the bus data transmission specification of the bridge chipset in the read-only memory; and causing the bridge chipset to respond to the first specification data and a second specification data representing the bus data transmission specification of the central processing unit transmitted to the bridge chipset to determine a workable bus data transmission specification of the bus, then exiting the system coordination state and performing data transmission using the workable bus data transmission specification.

Description

Data transmission specification determination method and bridge chipset and memory matching device

technical field

The present invention relates to a method for determining data transmission specifications and a bridge chip set and memory collocation device applied thereto, in particular to a method for determining data transmission specifications between a central processing unit and a bridge chip set in a computer system .

Background technique

The main board of the general computer sold on the market now is mainly composed of a central processing unit (Central Processing Unit, referred to as CPU), a chipset (chipset) and some peripheral circuits. The central processing unit is the entire computer. The core of the computer, the main job is to process and control the operation of each part of the entire computer, as well as to perform logical operations; while the chipset is responsible for connecting the operation between the central processing unit and other interface devices, the chip There are also many different ways to combine chipsets. At present, chipsets composed of two chips, the north bridge and the south bridge, are the common practice of most manufacturers on the market. According to different functions, among them The north bridge chip is responsible for connecting all the high-speed buses on the motherboard, while the south bridge chip is responsible for connecting the slower parts of the system.

Please refer to FIG. 1 , which is a circuit diagram of the configuration of components on a motherboard 1 . As shown in this figure, it can be seen that the mainboard 1 uses a single central processing unit 10 as the system architecture, and a chipset 2 is formed by a north bridge chip 20 and a south bridge chip 21, and the north bridge chip 20 passes through a front bus ( Front SideBus (FSB) 22 is in contact with the central processing unit 10. Generally speaking, the frequency of the front side bus 22 can be used under the common support of the central processing unit 10 and the north bridge chip 20, and in the host computer On the board 1, there is another graphics acceleration port (Accelerated Graphics Port, AGP) interface 31 via an AGP bus 311, and a random access memory (Random Access Memory, RAM) 32 via a memory bus 321, respectively connected to the north bridge chip 20; and in this figure, a peripheral component connection (Peripheral Component Interconnect, PCI) interface 30 is connected to the Southbridge chip 21 via a PCI bus 301, and an ISA (Industry Standard Architecture) interface 40, an IDE (Integrated Drive Electronics) interface 41, a USB (Universal Serial Bus) interface 42, a keyboard 43, a mouse 44 and other slower parts.

Therefore, the central processing unit 10 and the north bridge chip 20 must cooperate with each other to form a system of normal operation, and the collocation between the two at this part, for example, when the front bus transmission specifications are different from each other, that is, the bit of signal transmission When the width or speed (MHz) is not the same, there is no way for the CPU and Northbridge to communicate with each other. For example, a certain bridge chip can only be applied to a processor with a 64-bit front bus width produced by a certain manufacturer, but cannot be applied to a processor with a 32-bit front bus width produced by another manufacturer. Therefore, the similar situation has just caused the expense of needing to produce two types of bridge chips, and also caused the limitation of the compatibility of the central processing unit and the bridge chip and the inconvenience of matching, so, as far as the present is concerned, the central A protocol mechanism or coordination technique between the processing unit and the bridge chip is unquestionably required.

Please refer to FIG. 2(a) to FIG. 2(d), which are schematic block diagrams of a system in which the central processing unit 10 and the north bridge chip 20 are matched with different front bus widths, and the larger square in the figure The frame represents that a larger bit width can be used for signal transmission, and the smaller box containing a dotted line interval represents that the signal can only be transmitted with a smaller bit width; and part of the signal transmission is an address ( address) information, and the other part is a data (data) information, and an address bus 221 is used to transmit the address information, and a data bus 222 is used to transmit the data information. In Fig. 2 (a), since the central processing unit 10 and the north bridge chip 20 transmit signals with the width of the address bus 221 of 32 bits and the data bus 222 of 64 bits, the system formed can operate normally, In the same way, in Fig. 2 (b), although the bus width between the central processing unit 10 and the north bridge chip 20 is relatively small, because the bit width of the address information and the data information transmitted between the two is the same, it is still possible to compatible. However, it can be known from the above paragraph that if two signals are transmitted with different front-end bus widths, the system composed of the two will not be able to operate normally. That is, in FIG. 2( c), the data information of 64 bits transmitted by the north bridge chip 20 cannot allow the central processing unit 10 to transmit the data bus 222 with a width of 32 bits, and the address information in the central processing unit 10 is The address bus 221 is transmitted with a 13-bit width, but the north bridge chip 20 is transmitted with the address bus 221 with a 32-bit width. Therefore, under the usual system design, the central processing unit 10 and the north bridge chip 20 are mutually It cannot run normally between them, similar situation is shown in Fig. 2(d), and the same result is also obtained.

Due to the popularity of some personal mobile computing accessories on the market, such as: PDA (Personal Digital Assistant) or notebook computers, etc., and in order to cater to the concept of thinner and lighter volume, smaller printed circuits are required Boards or chips with fewer pins are used to match, so that the central processing units designed by various manufacturers also tend to have fewer and fewer pins. For example, the design with 32 bits as the width of the front bus, as shown in the figure The block diagram in 2(b) can represent it; on the other hand, in order to achieve better performance, some desktop application systems may have to use chips with more pins, such as the front bus width and At least 128-bit transmission mode instead of 64-bit or 32-bit; but when transmitting with different front-end bus widths, there will be problems like the above, so it is often easy to cause inconvenience to users, and it is very important for the manufacture of bridge chips. As far as manufacturers are concerned, they must produce different types of bridge chips in response to different types of central processing units. In this way, different types of bridge chips cannot support different types of central processing units, making these unusable bridge chips become waste in production. However, in the signal transmission design of the system, the one with the larger number of bits as the bus width is the one with the smaller number of bits that can support the bus width. In this way, how can this feature be used to solve the above-mentioned problems? The main purpose of the development of the present invention is to reduce the inconvenience and avoid unnecessary waste in production, so as to increase the effective operation rate of the system and the compatibility with each other.

Contents of the invention

In order to solve the above object, the present invention provides a method for determining data transmission specifications, which is applied to a central processing unit in a computer system, a bridge chip set and a bus connecting the two, and a bus electrically connected to the bridge chip set A read-only memory, the method includes the following steps: making the computer system enter a system coordination state; when the computer system enters the system coordination state, causing the bridge chipset to read a first specification data located in the read-only memory , the first specification data represents the bus data transmission specification of the bridge chip set; Two specification data, after determining a workable bus data transmission specification of the bus, jump out of the system coordination state and perform data transmission with the workable bus data transmission specification.

According to the above idea, in the method for determining the data transmission specification of the present invention, the system coordination state can be the reset state of the computer system.

According to the above idea, the method for determining the data transmission specification of the present invention, wherein the method for determining the workable bus data transmission specification of the bus includes the following steps: making the central processing unit send out the maximum A first signal of the bus data transmission specification of 1 bit to the bridge chipset; causing the bridge chipset responding to the first specification data to send a second signal to the central processing unit; and causing the central processing unit to receive the received signal The second signal judges, and the bridge chipset judges according to the received first signal, and after determining the operable bus data transmission specification of the bus, jumps out of the system coordination state and uses the operable bus data transmission specification for data transfer.

According to the above idea, in the method for determining data transmission specifications in the present invention, the bridge chip set can include a north bridge chip and a south bridge chip, and the north bridge chip is electrically connected to the central processing unit via the bus, and The south bridge chip is electrically connected to the read-only memory, and the north bridge chip is also electrically connected to the south bridge chip.

According to the above idea, the data transmission specification determination method of the present invention, wherein the north bridge chip can support a first bus data transmission specification and a second bus data transmission specification with the central processing unit, and the first specification data It represents a bus data transmission specification specified in the first bus data transmission specification and the second bus data transmission specification.

According to the idea above, in the method for determining data transmission specifications in the present invention, the first specification data is stored and recorded in the read-only memory, and when the computer system enters the system coordination state, the north bridge chip passes the south bridge chip Send a read signal to the read-only memory to read the first specification data representing the bus data transmission specification of the north bridge chip, so that the north bridge chip can determine the bus data transmission specification of the north bridge chip, and accordingly send The central processing unit sends out the second signal.

According to the above idea, in the method for determining data transmission specifications in the present invention, the first specification data representing the bus data transmission specifications of the North Bridge chip in the read-only memory can be modified so that the North Bridge chip can respond to the first specification data. Sending the second signal to the central processing unit according to a specification data.

According to the above idea, in the method for determining the data transmission specification of the present invention, the second specification data represents the bus data transmission specification of the maximum bit that the central processing unit can transmit and receive via the bus, and the first signal is sent accordingly .

According to the above idea, in the method for determining the data transmission specification of the present invention, the determination of the workable bus data transmission specification is based on the bus data transmission specification represented by the first signal and the bus data transmission specification represented by the second signal Select the bus data transmission specifications that can support each other between the two specifications.

According to the above idea, in the method for determining the data transmission specification of the present invention, after the data transmission specification of the operable bus has been determined and the system coordination state is exited, the bridging chipset can send a message to the central processing unit via the bus. A central processing unit resets the signal to notify the central processing unit that it can run, so that the central processing unit and the bridging chipset perform data transmission between the two with the working bus data transmission standard.

According to the above idea, in the method for determining the data transmission specification of the present invention, the bus data transmission specification can be the bus width, and when the bus data transmission specification is the bus width, the workable bus data transmission specification is a workable bus width

According to the above idea, in the method for determining the data transmission specification of the present invention, the bus data transmission specification can be the bus speed, and when the bus data transmission specification is the bus speed, the workable bus data transmission specification is a workable bus speed.

The present invention also provides a bridge chip set and memory matching device, which is applied to a central processing unit that sends a first signal through a first pin in a computer system and a central processing unit connected between the matching device and the central processing unit The bus, the device includes: a read-only memory, storing and recording a first specification data, the data represents a bus data transmission specification; and a bridge chip set, electrically connected to the read-only memory, the bridge chip set can respond The data of the first specification provided by the read-only memory sends a second signal to the central processing unit through a second pin provided on the bridge chipset and electrically connected to the central processing unit. The bridging chipset can receive the first signal sent by the central processing unit, and can judge the first signal to determine a workable bus data transmission specification of the bus.

According to the above idea, the bridge chip set and memory collocation device according to the present invention, wherein the bridge chip set includes: a north bridge chip, the first end of which is electrically connected to the first pin through the bus, and the second end of which is electrically connected to the first pin. Connected to the second pin, it can support a first bus data transmission specification and a second bus data transmission specification with the central processing unit, and the first specification data represents the first bus data transmission specification and A bus data transmission specification specified in the second bus data transmission specification; and a south bridge chip, the first end of which is electrically connected to the north bridge chip, and the second end of which is electrically connected to the read-only memory, capable of receiving the A read signal sent by the north bridge chip to read the first specification data in the ROM.

According to the above idea, in the bridge chip set and memory collocation device according to the present invention, the north bridge chip can read the first specification data by means of the read signal, so that the north bridge chip in the bridge chip set can determine the bus data transmission specification, and send the second signal to the central processing unit accordingly.

According to the above idea, in the bridge chip set and memory matching device of the present invention, the first specification data representing the bus data transmission specification of the Northbridge chip in the read-only memory can be modified so that the Northbridge chip can respond The second signal is sent to the central processing unit in response to the first specification data.

According to the above idea, in the bridge chip set and memory matching device of the present invention, the first signal represents the bus data transmission specification of the maximum bit that the central processing unit can transmit and receive via the bus.

According to the above idea, in the bridge chipset and memory collocation device described in the present invention, the determination of the data transmission specification of the operable bus is based on the data transmission specification of the bus represented by the first signal and the bus represented by the second signal The data transmission specification can select the bus data transmission specification that can support each other between the two.

The present invention can be better understood with the help of the following drawings and detailed description.

Description of drawings

Figure 1 is a circuit diagram of the configuration of each component on the motherboard.

2(a) to 2(d) are schematic block diagrams of a system in which a central processing unit and a north bridge chip are configured with different bus widths.

FIG. 3 is a schematic diagram of the configuration between the central processing unit and the bridge chip applied in the computer system according to the present invention.

FIG. 4 is a schematic block diagram of a preferred embodiment of the present invention.

5( a ) to FIG. 5( d ) are timing diagrams of signal generation in this preferred embodiment, based on the collocation of different bus data transmission specifications according to the present invention.

FIG. 6(a) and FIG. 6(b) are schematic block diagrams of the central processing unit and the bridge chipset configured with different bus data transmission specifications by the method of the present invention in this preferred embodiment.

Fig. 7 is a flowchart of a preferred embodiment of the present invention.

Wherein, the reference signs are explained as follows:

1 motherboard 10 central processing unit

20 North Bridge Chips 21 South Bridge Chips

2 chipset 22 front side bus

221 address bus 222 data bus

30 Peripheral component connection interface 301 PCI bus

31 graphics acceleration port interface 311 AGP bus

32 Random Access Memory 321 Memory Bus

40 ISA interface 41 IDE interface

42 USB interface 43 keyboard

44 mouse 50 central processing unit

501 first pin 51 bridge chipset

512 North Bridge Chip 513 South Bridge Chip

511 second pin 52 bus

HAm first signal HAn second signal

53 ROM DWNCMD read signal

RDDATA data receive signal

CPURESET Central processing unit reset signal

PCIRESET peripheral component connection reset signal

Detailed ways

Please refer to FIG. 3 , which is a schematic configuration diagram of a central processing unit 50 , a bridge chipset 51 and a bus 52 connecting them in a computer system. In a preferred embodiment of the present invention, the central processing unit 50 and the bridge chipset 51 are arranged on a motherboard (not shown in the figure) as described in the prior art, and the bridge chipset 51 Just can comprise the north bridge chip etc. in the chip set described in the prior art, as can be seen from Fig. 3, between this central processing unit 50 and this bridging chip set 51 both can be through this bus line 52 that all are electrically connected to each other. Send and receive signals. Since the central processing unit 50 and the bridging chipset 51 are integrated circuit chip structures, there are a lot of pins on the outside as interfaces for sending or sending signals.

It can be seen from the description of the prior art that the bus 52 that is configured between the central processing unit 50 and the bridge chipset 51, when the bus widths of the maximum bits that can be transmitted by the two are different, that is, the maximum bits that can be transmitted are different. When same, just can't make this central processing unit 50 and this bridging chipset 51 generate connection with each other; Only half of the transmitted data will be received and the other half will be lost. However, if both parties can utilize the characteristic that the one with the larger number of bits of the bus width can support the smaller one of the bus width, then the central processing unit 50 can coordinate with the bridge chipset 51 to form a same bus Width for transmission, so the above-mentioned problems can be solved.

Please refer to FIG. 4 , which is a schematic block diagram of a preferred embodiment of the present invention. Firstly, make the computer system enter a system coordination state, such as a system reset state, and then respond to the computer system entering the system coordination state, make the bridge chipset 51 read the information that is electrically connected to the bridge chipset 51. A first specification data stored in the read-only memory 53, and the first specification data represents the bus data transmission specification of the bridge chip set 51, and finally, the bridge chip set 51 responds to the first specification data and sends to A second specification data representing the bus data transmission specification of the central processing unit 50 in the bridge chipset 51, after determining a workable bus data transmission specification of the bus 52, jump out of the system coordination state and use the workable The bus data transfer specification performs data transfer. In this preferred embodiment, the second specification data represents the bus data transmission specification of the maximum bit that the central processing unit 50 can transmit and receive via the bus 52, so the determination of the workable bus data transmission specification on the one hand It is to make the central processing unit 50 send a first signal HAm representing the bus data transmission specification of the maximum bit of the central processing unit 50 to the bridge chipset 51 according to the second specification data, and respond to the first signal HAm on the other hand. The bridge chipset 51 of specification data also sends a second signal HAn to the central processing unit 50, so that the central processing unit 50 can receive the second signal HAn and the bridge chipset 51 according to the received first The signal HAm is judged, so the bus data transmission specification that can be supported between the first signal HAm and the second signal HAn is selected as a representative, and then the workable bus data transmission specification of the bus 52 is determined, and then jump out The system coordinates state and performs data transmission with the operative bus data transmission specification.

As can be seen from FIG. 4, the central processing unit 50 sends the first signal HAm to the bridge chip set 51 through a first pin 501 provided thereon, and the bridge chip set 51 is electrically connected to the bridge chip set 51. ROM 53, wherein the ROM 53 stores and records the first specification data (not shown) representing a bus data transmission specification, so the bridge chipset 51 can respond to the ROM 53 provided The first specification data, and then send the second signal HAn to the central processing unit 50 through a second pin 511 provided thereon and electrically connected to the central processing unit 50 . The first signal HAm can be sent via one of the pin groups in which the central processing unit 50 and the bridge chipset 51 are connected through the bus 52 via the inventive concept of the present invention, preferably In the embodiment, even if the first pin 501 is used for its purpose, the same is true for the second signal HAn on the other hand.

Also shown in FIG. 4 , the bridge chip set 51 can include a north bridge chip 512 and a south bridge chip 513, wherein the first end of the north bridge chip 512 is electrically connected to the central processing unit 50 via the bus 52 The first pin 501, and its second end is electrically connected to the second pin 511, the north bridge chip 512 can support a variety of bus data transmission specifications with the central processing unit 50, and the first specification The data represents a bus data transmission specification specified in the various bus data transmission specifications of the north bridge chip 512; the first end of the south bridge chip 513 is electrically connected to the north bridge chip 512, and its second end is electrically connected to the north bridge chip 512. The ROM 53 . In this preferred embodiment, after the computer system enters the system coordination state, the north bridge chip 512 can send a read signal DWNCMD to the read-only memory 53 through the south bridge chip 513 to read the Read the first specification data representing the bus data transmission specification of the north bridge chip 512 in the read memory 53, and make the north bridge chip 512 determine the bus data transmission specification through a data receiving signal RDDATA, and send the bus data transmission specification to the central processing unit 50 accordingly. The second signal HAn. And finally when the data transmission specification of the workable bus has been determined, and after jumping out of the system coordination state, the bridge chipset 51 can send a central processing unit reset signal CPURESET to the central processing unit 50 via the bus 52, to Informing the central processing unit 50 that it can run, so that the central processing unit 50 and the bridge chipset 51 perform data transmission between the two according to the working bus data transmission specification.

In this preferred embodiment, the bus data transmission specification can be determined as the bus width, and when the response bus data transmission specification is the bus width, the workable bus data transmission specification obtained is just a workable bus width; in the same way , the bus data transmission specification can be set as the bus speed, and when the bus data transmission specification is the bus speed, the obtained workable bus data transmission specification is a workable bus speed. As can be seen from the above, before the central processing unit 50 and the bridge chipset 51 actually transmit data, the function of the first signal HAm and the second signal HAn is to inform the other party what its own data transmission specification is, so when After exchanging signals, any party can know the compatibility between each other; for example, if it can transmit 64-bit bus width itself, but the received signal from the other party can only transmit 32 bits, according to the comparison of the number of bits The bus width of the larger one can support the bus width of the one with the smaller number of bits, and the bus widths of the two coordinate with each other to operate at the smaller side of 32 bits. In addition, because the north bridge chip 512 in the present invention can support multiple bus data transmission specifications with the central processing unit 50, for example, it can simultaneously support the 32-bit data transmission specification of the smaller specification and the 64-bit data transmission specification of the larger specification. Bit data transmission specifications, etc., and in the known technology, we can easily use the program set by the system to modify the first specification data representing the bus data transmission specification of the Northbridge chip 512 in the read-only memory 53, The north bridge chip 512 can send the second signal HAn to the central processing unit 50 in response to the first specification data, so that the configuration required by the user can be combined, so that the manufacturer does not need to match known specifications of different specifications in order to respond The market supply and demand of the central processing unit, and increase the cost to develop different production lines to manufacture the known bridge chipset, which can solve the problems of unnecessary waste and inconvenience in production and inventory; at the same time, it can also be used according to the present invention The method and device, through the signal exchange between the central processing unit 50 and the bridging chipset 51, can avoid the situation of not being able to operate normally due to mutual compatibility problems as described in the prior art, therefore, successfully Achieved the main purpose of the development of the present invention.

Please refer to Fig. 5(a) to Fig. 5(d), for the central processing unit 50 and the bridging chipset 51 in this preferred embodiment, the signal generated by the collocation of different bus data transmission specifications according to the present invention timing diagram. In this preferred embodiment, we send a peripheral component connection reset signal PCIRESET by a peripheral component connection interface (not shown in the figure), so that the computer system enters the system coordination state, because the first signal HAm The encoding output mode of the second signal HAn in the computer system can be a high-level voltage representing a larger bus width (or bus speed), or a low-level voltage representing a smaller bus width (or bus speed) , and in this preferred embodiment of the present invention, it is defined that the larger specification represents a high-level voltage, and the smaller specification represents a low-level voltage. It can be seen from Fig. 5 (a) to (d) that if the first signal HAm and the second signal HAn show a straight line with a high level, it means that the bus data transmission specification is relatively large; otherwise, If it appears as a segment with a level drop, it means that the bus data transmission specification is relatively small, so four possible combinations are shown in Figure 5(a) to (d), and in Figure 5(a) to Figure 5 In 5(c), it is determined that the central processing unit 50 and the bridge chipset 51 transmit signals to each other with a low-level voltage of the smaller bus data transmission specification, and in FIG. 5(d), it is determined that The high-level voltage of the larger bus data transmission specification is used for the transmission of mutual signals. However, no matter what the final data transmission specification of the workable bus is, the central processing unit 50 and the bridge chipset 51 will each process data with their own original performance.

As can be seen from FIG. 5(a) to FIG. 5(d), in this preferred embodiment, it is defined that the peripheral component connection reset signal PCIRESET is issued when the time zone is 1 to enter the system coordination state, and at time When the section is 2, the north bridge chip 512 can send the read signal DWNCMD to the read-only memory 53 through the south bridge chip 513 (it can be seen from these figures that the signal also includes two parts of a DWNWR and a DWNADDR), so that Read the first specification data representing the bus data transmission specification of the north bridge chip 512 in the read-only memory 53, then when the time zone is 5, the south bridge chip 513 can receive the signal RDDATA through the data to make The north bridge chip 512 is able to determine the bus data transmission specification, wherein the kth bit (that is, RDDATAk shown in these figures) on the data receiving signal RDDATA just records the first specification data, marking the north bridge chip 512. The specified bus data transmission specification, and similarly, if RDDATAk is displayed as a high-level voltage, it means that it can run on a larger bus data transmission specification; Bus data transfer specification. When the time zone is 7, the central processing unit 50 and the bridge chipset 51 simultaneously send out the first signal HAm and the second signal HAn to notify each other, and determine the workable bus data transmission in the above-mentioned manner After the specification, it is defined that when the time interval is 8, the bridging chipset 51 sends the CPURESET signal CPURESET to the CPU 50 to notify the CPU 50 that it can run. As for the encoding output mode of the first signal HAm and the second signal HAn in the computer system, it can also be changed to a low level voltage representing a larger bus width (or bus speed), and a smaller bus width (or bus speed) to represent a smaller bus width (or bus speed). Bus speed) is a high-level voltage, or when the classification of the bus width exceeds two types, it can be represented by a serial or parallel voltage level signal, for example, 00 represents a low bus width, 01 represents a medium bus width, And 10 represents a high bus width, but such changes should be common technical means, so they will not be repeated here.

Please refer to Fig. 6 (a) and Fig. 6 (b), it is in this preferred embodiment, this central processing unit 50 and this bridging chipset 51 carry out the method of different bus data transmission standard configurations with the method of the present invention Box schematic. In Fig. 6 (a) and Fig. 6 (b), the north bridge chip 512 in the bridge chipset 51 is all designed to support multiple bus data transmission specifications with the central processing unit 50, so it is better Embodiments For example, 32 bits are used to represent the smaller bus data transmission specification, and 64 bits are used to represent the larger bus data transmission specification. Therefore, in FIG. 6(a) and FIG. 6(b) In this example, the north bridge chip 512 can simultaneously support 32-bit and 64-bit bus data transmission specifications; The first specification data (not shown) represents different bus data transmission specifications, and the first specification data in Figure 6 (a) represents a larger 64-bit specification, so its North Bridge chip 512 is designated to run On 64 bits, and the first specification data in Fig. 6 (b) represents 32 bits with a smaller specification, so its North Bridge chip 512 is designated to run on 32 bits, so, through the previously described different specifications The known bridge chip set needs to be manufactured in different production lines to match the known central processing unit. In this preferred embodiment, it is developed to integrate multiple bus data transmission specifications on the same component, and only the read-only The first specification data representing the bus data transmission specification of the northbridge chip 512 in the memory 53 is modified to obtain the configuration required by the user. It can be seen that the present invention can indeed reduce cost overhead and many inconvenience problems, and successfully Reached the development purpose of the present invention.

Please refer to FIG. 7, which is a flowchart of a preferred embodiment of the present invention. First, the computer system enters the system coordination state, and secondly, the bridge chip set 51 reads and responds to the first specification data representing the bus data transmission specification of the bridge chip set 51 in the read-only memory 53, and sends a second signal HAn to the central processing unit Unit 50, and the central processing unit 50 sends the first signal HAm representing the bus data transmission specification of the maximum bit of the central processing unit 50 to the bridge chipset 51 according to the second specification data, and then the central processing unit 50 sends the first signal HAm to the bridge chipset 51 according to the second specification data received. signal HAn and the bridge chipset 51 judges according to the received first signal HAm to determine the workable bus data transmission specification of the bus 52, jump out of the system coordination state and perform data transmission with the workable bus data transmission specification, and finally, bridge The chipset 51 can send a central processing unit reset signal CPURESET to the central processing unit 50 via the bus 52 to notify the central processing unit 50 that it can run.

To sum up, using the technology of the present invention can reduce or even avoid the incompatibility probability of producing bridge chipsets of different specifications in response to central processing units of different specifications when manufacturing bridge chipsets. In this way, a certain A standard bridge chipset can support central processing units of different specifications, which can solve the inconvenience in use and unnecessary waste in production as described in the previous technology, and increase the effective operating rate of the system and mutual compatibility. Therefore, The main purpose of developing the present invention is indeed achieved. However, the present invention may be subject to some modifications at the discretion of those skilled in the art.

Claims (11)

1. A method for determining data transmission specifications, applied to a central processing unit in a computer system, a bridge chip set and a bus connected between the two and a read-only memory electrically connected to the bridge chip set, the method Contains the following steps: the computer system enters a system coordination state; When the computer system enters the system coordination state, the bridge chipset reads a first specification data located in the ROM, the first specification data represents the bus data transmission specification of the bridge chipset; and After the bridge chipset responds to the first specification data and a second specification data representing the bus data transmission specification of the central processing unit transmitted to the bridge chipset to determine a workable bus data transmission specification of the bus, Jump out of the system coordination state and perform data transmission with the workable bus data transmission specification. 2. The method for determining data transmission specifications according to claim 1, wherein the system coordination state is a reset state of the computer system. 3. The method for determining data transmission specifications according to claim 1, wherein the method for determining the workable bus data transmission specifications of the bus comprises the following steps: The central processing unit sends a first signal representing the maximum bit bus data transmission specification to the bridge chipset according to the second specification data; the bridging chipset responding to the first specification data sends a second signal to the central processing unit; and The central processing unit judges according to the received second signal, and the bridging chipset judges according to the received first signal, and after determining the operable bus data transmission specification of the bus, jumps out of the system coordination state and Data transmission is performed with the operable bus data transmission specification. 4. The method for determining data transmission specifications according to claim 3, wherein the bridge chipset includes a north bridge chip and a south bridge chip, the north bridge chip is electrically connected to the central processing unit via the bus, and the south bridge chip is electrically connected to the central processing unit. The electrical signal of the chip is connected to the read-only memory, and the electrical signal is also connected between the north bridge chip and the south bridge chip, and the north bridge chip supports a first bus data transmission specification and a second bus with the central processing unit data transmission specification, and the first specification data represents a bus data transmission specification specified in the first bus data transmission specification and the second bus data transmission specification, and the first specification data is stored and recorded in the read-only In the memory, when the computer system enters the system coordination state, the north bridge chip sends a read signal to the read-only memory through the south bridge chip to read the first bus data transmission specification representing the north bridge chip. A specification data, the north bridge chip can determine the bus data transmission specification of the north bridge chip, and send the second signal to the central processing unit accordingly, and through the bus data transmission specification representing the north bridge chip in the read-only memory The first specification data is modified, and the north bridge chip sends the second signal to the central processing unit in response to the first specification data. 5. The method for determining data transmission specifications according to claim 3, wherein the second specification data represents the bus data transmission specification of the maximum bit that the central processing unit can transmit and receive via the bus, and sends the first signal accordingly , and the determination of the operable bus data transmission specification is based on the bus data transmission specification that can support each other between the bus data transmission specification represented by the first signal and the bus data transmission specification represented by the second signal select. 6. The method for determining data transmission specifications according to claim 3, wherein after the data transmission specification of the operative bus has been determined and the system coordination state is exited, the bridging chipset sends a message to the central processing unit via the bus. The central processing unit resets the signal to notify the central processing unit that it can run, and the central processing unit and the bridging chipset perform data transmission between the two according to the working bus data transmission specification. 7. The method for determining a data transmission specification according to claim 1, wherein the bus data transmission specification is a bus width, and when the bus data transmission specification is a bus width, the workable bus data transmission specification is a workable bus width , and the bus data transmission specification can also be a bus speed, and when the bus data transmission specification is a bus speed, the workable bus data transmission specification is a workable bus speed. 8. A bridge chip set and memory collocation device, applied to a central processing unit that sends a first signal through a first pin in a computer system and a bus that is connected between the collocation device and the central processing unit, The unit contains: The read-only memory stores and records a first specification data, which represents a bus data transmission specification; and A bridge chip set electrically connected to the read-only memory, the bridge chip set responds to the first specification data provided by the read-only memory, through a first bridge chip set installed on the bridge chip set and electrically connected to the central processing unit Two pins, sending a second signal to the central processing unit, the bridge chipset can receive the first signal sent by the central processing unit, and can judge the first signal to determine the An operational bus data transfer specification for the bus. 9. The bridge chip set and memory matching device according to claim 8, wherein the bridge chip set comprises: A north bridge chip, the first end of which is electrically connected to the first pin via the bus, and the second end is electrically connected to the second pin, supporting a first bus data transmission specification with the central processing unit and a second bus data transmission specification, and the first specification data represents a bus data transmission specification specified in the first bus data transmission specification and the second bus data transmission specification; and A south bridge chip, its first end is electrically connected to the north bridge chip, and its second end is electrically connected to the read-only memory, and can receive a read signal sent by the north bridge chip to read the read-only memory The first specification data of . 10. The bridge chip set and memory matching device according to claim 9, wherein the north bridge chip reads the first specification data by means of the read signal, so that the north bridge chip in the bridge chip set can determine the bus Data transmission specification, and send the second signal to the central processing unit accordingly, and modify the first specification data representing the bus data transmission specification of the Northbridge chip in the read-only memory, so that the Northbridge chip can The second signal is sent to the central processing unit in response to the first specification data. 11. The bridge chipset and memory matching device according to claim 8, wherein the first signal represents the bus data transmission specification of the maximum bit that the central processing unit can transmit and receive via the bus, and the workable bus data transmission The determination of the specification is to select the mutually supportable bus data transmission specification between the bus data transmission specification represented by the first signal and the bus data transmission specification represented by the second signal.

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