[go: up one dir, main page]

CA2145219A1 - Pipeline system including inverse modeller stage, inverse cosine transform stage, and processing stage - Google Patents

Pipeline system including inverse modeller stage, inverse cosine transform stage, and processing stage

Info

Publication number
CA2145219A1
CA2145219A1 CA002145219A CA2145219A CA2145219A1 CA 2145219 A1 CA2145219 A1 CA 2145219A1 CA 002145219 A CA002145219 A CA 002145219A CA 2145219 A CA2145219 A CA 2145219A CA 2145219 A1 CA2145219 A1 CA 2145219A1
Authority
CA
Canada
Prior art keywords
stage
inverse
cosine transform
processing
pipeline system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002145219A
Other languages
French (fr)
Other versions
CA2145219C (en
Inventor
Adrian Philip Wise
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Discovision Associates
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB9405914A external-priority patent/GB9405914D0/en
Application filed by Individual filed Critical Individual
Publication of CA2145219A1 publication Critical patent/CA2145219A1/en
Application granted granted Critical
Publication of CA2145219C publication Critical patent/CA2145219C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3871—Asynchronous instruction pipeline, e.g. using handshake signals between stages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3873—Variable length pipelines, e.g. elastic pipeline
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G06F9/3895—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/13—Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H04N19/91—Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Computer Hardware Design (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Image Processing (AREA)
  • Complex Calculations (AREA)
  • Television Systems (AREA)
  • Advance Control (AREA)
  • Compression Of Band Width Or Redundancy In Fax (AREA)
  • Color Television Systems (AREA)

Abstract

A pipeline system processes data in a series of stages which include an inverse modeller stage, an inverse discrete cosine transform stage, and a processing stage. The processing stage is positioned between the inverse modeller stage and the inverse discrete cosine transform stage and responds to tokens for processing data. The tokens each include a plurality of data words. Extension indicators in each word indicate the presence or absence of additional words in the token, thereby permitting the tokens to be unlimited in length.
CA002145219A 1994-03-24 1995-03-22 Pipeline system including inverse modeller stage, inverse cosine transform stage, and processing stage Expired - Fee Related CA2145219C (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB9405914A GB9405914D0 (en) 1994-03-24 1994-03-24 Video decompression
GB9405914.4 1994-03-24
GB9504047.3 1995-02-28
GB9504047A GB2288521B (en) 1994-03-24 1995-02-28 Reconfigurable process stage

Publications (2)

Publication Number Publication Date
CA2145219A1 true CA2145219A1 (en) 1995-09-25
CA2145219C CA2145219C (en) 2001-11-27

Family

ID=26304581

Family Applications (3)

Application Number Title Priority Date Filing Date
CA002145549A Expired - Lifetime CA2145549C (en) 1994-03-24 1995-03-22 Multi-standard configuration
CA002145219A Expired - Fee Related CA2145219C (en) 1994-03-24 1995-03-22 Pipeline system including inverse modeller stage, inverse cosine transform stage, and processing stage
CA002145426A Abandoned CA2145426A1 (en) 1994-03-24 1995-03-23 Pipeline processing machine, related system and multi-standard decoder including reconfigurable processing stages and method relating thereto

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CA002145549A Expired - Lifetime CA2145549C (en) 1994-03-24 1995-03-22 Multi-standard configuration

Family Applications After (1)

Application Number Title Priority Date Filing Date
CA002145426A Abandoned CA2145426A1 (en) 1994-03-24 1995-03-23 Pipeline processing machine, related system and multi-standard decoder including reconfigurable processing stages and method relating thereto

Country Status (5)

Country Link
JP (4) JP3302527B2 (en)
KR (1) KR100291532B1 (en)
CN (2) CN1137212A (en)
CA (3) CA2145549C (en)
GB (1) GB2288521B (en)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2794601B1 (en) * 1999-06-02 2001-07-27 Dassault Automatismes COMMUNICATION DEVICE FOR COLLECTIVE INFORMATION RECEPTION, IN PARTICULAR OF DIGITAL TELEVISION IMAGES AND / OR MULTIMEDIA DATA
EP1148727A1 (en) * 2000-04-05 2001-10-24 THOMSON multimedia Method and device for decoding a digital video stream in a digital video system using dummy header insertion
KR100354768B1 (en) 2000-07-06 2002-10-05 삼성전자 주식회사 Video codec system, method for processing data between the system and host system and encoding/decoding control method in the system
US8284844B2 (en) 2002-04-01 2012-10-09 Broadcom Corporation Video decoding system supporting multiple standards
KR100722428B1 (en) * 2005-02-07 2007-05-29 재단법인서울대학교산학협력재단 Reconfigurable array structure with resource sharing and pipelining configuration
US7873105B2 (en) 2005-04-01 2011-01-18 Broadcom Corporation Hardware implementation of optimized single inverse quantization engine for a plurality of standards
KR100711088B1 (en) * 2005-04-13 2007-04-24 광주과학기술원 Integer Converter for Moving Picture Encoder
KR100718135B1 (en) 2005-08-24 2007-05-14 삼성전자주식회사 Apparatus and method for image prediction for multi-format codecs and apparatus and method for image encoding / decoding using same
KR101354659B1 (en) * 2006-11-08 2014-01-28 삼성전자주식회사 Method and apparatus for motion compensation supporting multicodec
JP5698428B2 (en) * 2006-11-08 2015-04-08 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． Motion compensation method, recording medium, and motion compensation device
KR101553648B1 (en) 2009-02-13 2015-09-17 삼성전자 주식회사 Processor with reconfigurable architecture
KR101532821B1 (en) * 2010-04-02 2015-06-30 후지쯔 가부시끼가이샤 Apparatus and method for orthogonal cover code(occ) generation, and apparatus and method for occ mapping
US8413166B2 (en) * 2011-08-18 2013-04-02 International Business Machines Corporation Multithreaded physics engine with impulse propagation
US10219006B2 (en) * 2013-01-04 2019-02-26 Sony Corporation JCTVC-L0226: VPS and VPS_extension updates
US9395990B2 (en) * 2013-06-28 2016-07-19 Intel Corporation Mode dependent partial width load to wider register processors, methods, and systems
JP6223323B2 (en) * 2014-12-12 2017-11-01 Ｎｔｔエレクトロニクス株式会社 Decimal pixel generation method
WO2017007546A1 (en) * 2015-07-03 2017-01-12 Intel Corporation Apparatus and method for data compression in a wearable device
CN107729989B (en) * 2017-07-20 2020-12-29 安徽寒武纪信息科技有限公司 Device and method for executing artificial neural network forward operation
CN109901044B (en) * 2017-12-07 2021-11-12 英业达科技有限公司 Central processing unit differential test system of multiple circuit boards and method thereof
DE102019208121A1 (en) * 2019-06-04 2020-12-10 Continental Automotive Gmbh Active data generation taking into account uncertainties
CN113591795B (en) * 2021-08-19 2023-08-08 西南石油大学 Lightweight face detection method and system based on mixed attention characteristic pyramid structure

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0576749B1 (en) * 1992-06-30 1999-06-02 Discovision Associates Data pipeline system
US4680581A (en) * 1985-03-28 1987-07-14 Honeywell Inc. Local area network special function frames
US5325092A (en) * 1992-07-07 1994-06-28 Ricoh Company, Ltd. Huffman decoder architecture for high speed operation and reduced memory
US5298896A (en) * 1993-03-15 1994-03-29 Bell Communications Research, Inc. Method and system for high order conditional entropy coding
US5699460A (en) * 1993-04-27 1997-12-16 Array Microsystems Image compression coprocessor with data flow control and multiple processing units

Also Published As

Publication number Publication date
CA2145426A1 (en) 1995-09-25
CA2145219C (en) 2001-11-27
JPH0918871A (en) 1997-01-17
CA2145549A1 (en) 1995-09-25
JPH08116260A (en) 1996-05-07
KR100291532B1 (en) 2001-06-01
KR950033896A (en) 1995-12-26
CA2145549C (en) 2001-02-20
CN1235483A (en) 1999-11-17
CN1137212A (en) 1996-12-04
JPH11266460A (en) 1999-09-28
GB9504047D0 (en) 1995-04-19
JP3302527B2 (en) 2002-07-15
GB2288521A (en) 1995-10-18
GB2288521A8 (en) 1996-04-15
GB2288521B (en) 1998-10-14
JPH0870453A (en) 1996-03-12

Similar Documents

Publication Publication Date Title
CA2145219A1 (en) Pipeline system including inverse modeller stage, inverse cosine transform stage, and processing stage
DE69626620D1 (en) Data processing in systems that show a visual representation of a physical environment
AU676815B2 (en) Data processing and operating system incorporating dynamic binding across two or more processors
DE69230897D1 (en) Discrete / inversely discrete cosine transformation processor and data processing method
DE69424610D1 (en) Data processing system and method
DE69531704D1 (en) TRANSACTION PROCESSING SYSTEM AND IMPLEMENTATION METHOD
GB2288677B (en) Pipeline processing device, clipping processing device, three-dimensional simulator device and pipeline processing method
NL1011655A1 (en) Ventilated cage and rack system.
DE3750135D1 (en) Word processing system and method for checking the correct and consistent use of units and chemical formulas in a word processing system.
DE69032862D1 (en) Intelligent input / output processor and data processing system
EP0465035A3 (en) Transaction processing system and method
DE3650335D1 (en) COMPUTING PROCESS AND DEVICE FOR FINAL FIELD MULTIPLICATION.
DE69028373D1 (en) Multi-stage locking system and method
EP0676706A3 (en) Object oriented data access and analysis system.
KR20010012703A (en) Data processing device and method of computing the cosine transform of a matrix
DE59203085D1 (en) Device for reactive ion etching and plasma-assisted CVD processes.
DE69507975D1 (en) Processing system and process
ITTO920140A0 (en) ELECTRONIC VOTING SYSTEM AND RELATED METHOD.
CA2326152A1 (en) Indication of failure in a transaction processing system
DE69219166D1 (en) Data processing system and method for various data formats
EP0588726A3 (en) Discrete cosine transformation system and inverse discrete cosine transformation system, having simple structure and operable at high speed.
EP0649096A3 (en) Shared memory system and arbitration method and system therefor.
DE69230901D1 (en) Graphic data processing system and method
AU5785690A (en) Data transmission method and data processing system using the same
FR2718864B1 (en) Digital processing device with minimum and maximum search instructions.

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed