JP6223323B2 - Decimal pixel generation method - Google Patents

Description

The present invention relates to HEVC and H.264. The present invention relates to a fractional pixel generation method capable of sharing the fractional pixel generation process of H.264 / AVC.

  HEVC is H.264. H.264 / AVC (hereinafter referred to as H.264) is a next-generation video coding standard system with higher coding efficiency. In any method, motion prediction / motion compensation using decimal pixels is performed to improve prediction efficiency (see, for example, Non-Patent Documents 1 and 2).

  FIG. 9 is a diagram showing a conventional decimal pixel generation circuit of HEVC. The 8-tap horizontal filter 11 receives the reference image and generates a horizontal fractional pixel (1/2 pixel accuracy, 1/4 pixel accuracy). Next, the 8-tap vertical filter 12 inputs horizontal fractional pixels via the vertical filter input buffer 13 to generate vertical fractional pixels (1/2 pixel accuracy, 1/4 pixel accuracy).

  FIG. 2 is a diagram illustrating a H.264 conventional decimal pixel generation circuit. FIG. A 6 tap 1/2 pixel filter 14 receives the reference image and generates a decimal pixel with 1/2 pixel accuracy. Next, the 2 tap 1/4 pixel filter 15 receives the 1/2 pixel precision decimal pixel via the 1/4 pixel filter input buffer 16 and generates a 1/4 pixel precision decimal pixel.

"ITU-T H.265 | ISO / IEC 23008-2 High Efficiency Video Coding" ITU-T, January 2013 "ITU-T Rec. H.264 | ISO / IEC 14496-10 Advanced Video Coding" ITU-T, May 2003

  HEVC and H.C. There is a request to enable H.264 processing to be executed by one processing system. In particular, since the generation of decimal pixels used for motion prediction is required to be implemented by hardware rather than processor processing for speeding up, HEVC and H. It is desired to share the H.264 decimal pixel generation process. However, as described above, HEVC and H.P. In H.264, one of the obstacles is that the decimal pixel generation method is different.

  The present invention has been made in order to solve the above-described problems, and the object thereof is HEVC and H.264. It is to obtain a decimal pixel generation circuit capable of sharing H.264 decimal pixel generation processing.

The decimal pixel generation method according to the present invention includes a horizontal sub-pixel generation unit that generates a horizontal sub-pixel by inputting a reference image, and generates a vertical sub-pixel by inputting the reference image and the horizontal sub-pixel. A fractional pixel generation circuit comprising: a fractional pixel generation circuit including a vertical direction fractional pixel generation unit; a horizontal direction fractional pixel generation unit; and a coefficient selection unit that selects a filter coefficient of the vertical direction fractional pixel generation unit. In the fractional pixel generation method for performing the process of generating, when the fractional pixel generation circuit generates a fractional pixel conforming to HEVC from the reference image, the coefficient selection unit is -1, 4, -11, 40, 40. , -11, 4, −1, and a second filter coefficient consisting of −1, 4, −10, 58, 17, -5, 1, 0, and the decimal Pixel generation H. road from the reference image H.264 / AVC-compliant decimal pixels are generated, a third filter coefficient consisting of 1, -5, 20, 20, -5, 1, 0, 0, 0, 1, 1, 0, 0, 1, select one of the fourth filter coefficient consisting of 1,0, when the sub-pixel generating circuit generates a decimal pixel conforming to HEVC from the reference image, the horizontal sub-pixel generation unit has been entered From the reference image , a horizontal ½ pixel is generated based on the first filter coefficient, and a horizontal ¼ pixel is generated from the input reference image based on the second filter coefficient. and generating the horizontal sub-pixel of the vertical direction sub-pixel generation unit, from the horizontal sub-pixel and input the reference image, the vertical half-pixel based on the first filter coefficients Generated and entered H. from the horizontal sub-pixel and the reference image, and a step of generating a vertical quarter-pixel based on the second filter coefficients, from the sub-pixel generation circuit said reference image When generating the decimal pixels conforming to 264 / AVC, the horizontal sub-pixel generation unit, from the inputted reference image, to generate a horizontal ½ pixel on the basis of the third filter coefficients is inputted Generating a horizontal ¼ pixel from the reference image and the generated horizontal ½ pixel based on the fourth filter coefficient to generate all the horizontal decimal pixels; direction fractional pixel generation unit, from the horizontal sub-pixel and input the reference image, the third generates vertical half-pixel based on the filter coefficients, the horizontal fractional and input the reference image from the vertical half-pixel and the generated pixel, and a step of generating a vertical quarter-pixel on the basis of the fourth filter coefficient, the horizontal sub-pixel whereas pel A sub-pixel in the horizontal direction, the vertical direction sub-pixel is characterized by a sub-pixel in the vertical direction with respect to the integer pixel and the horizontal sub-pixel.

  In accordance with the present invention, HEVC and H.C. H.264 decimal pixel generation processing can be shared.

It is a figure which shows the decimal pixel generation circuit which concerns on embodiment of this invention. It is a figure which shows the position of a decimal pixel. H. 2 is a flowchart of a conventional processing procedure of H.264 decimal pixel generation. It is a figure which shows the 1/2 pixel production | generation method of the conventional process sequence. It is a figure which shows the 1/4 pixel production | generation method of the conventional process sequence. H. in the embodiment of the present invention. 3 is a flowchart of a H.264 decimal pixel generation processing procedure. H. in the embodiment of the present invention. It is a figure which shows a H.264 horizontal direction decimal pixel production | generation method. H. in the embodiment of the present invention. 2 is a diagram illustrating a H.264 vertical-direction decimal pixel generation method. FIG. It is a figure which shows the conventional decimal pixel generation circuit of HEVC. H. 2 is a diagram illustrating a H.264 conventional decimal pixel generation circuit. FIG.

  FIG. 1 is a diagram showing a decimal pixel generation circuit according to an embodiment of the present invention. The 8-tap horizontal filter 1 receives a reference image and generates a horizontal fractional pixel. The 8-tap vertical filter 2 inputs horizontal fractional pixels via the vertical filter input buffer 3 and generates vertical fractional pixels. The coefficient selection units 4 and 5 are configured so that the reference image is HEVC or H.264. H.264, the filter coefficients of the horizontal filter 1 and the vertical filter 2 are selected.

  When the reference image is HEVC, the horizontal filter 1 and the vertical filter 2 can be processed as in the conventional circuit of HEVC shown in FIG. In the coefficient selection units 4 and 5, the reference image is H.264. Even in the case of H.264, filter coefficients are selected so that the processing can be performed by the horizontal filter 1 and the vertical filter 2. Table 1 shows specific examples of filter coefficients.

  Subsequently, the reference image is H.264. The processing procedure of this embodiment in the case of H.264 is described in H.264. This will be described in comparison with the H.264 conventional processing procedure. FIG. 2 is a diagram showing the position of the decimal pixel.

FIG. 2 is a flowchart of a conventional processing procedure of H.264 decimal pixel generation. First, 1/2 pixel is generated (step S11), and then 1/4 pixel is generated (step S12). FIG. 4 is a diagram showing a 1/2 pixel generation method in the conventional processing procedure. Decimal pixels at positions b, h, j are generated as 1/2 pixels. The calculation formula of 1/2 pixel is as follows.
b ₁ = (E-5 ^* F + 20 ^* G + 20 ^* H-5 ^* I + J)
h ₁ = (A-5 ^* C + 20 ^* G + 20 ^* M-5 ^* R + T)
b = Clip ((b ₁ +16) >> 5)
h = Clip ((h ₁ +16) >> 5)
^{_{j 1 = (cc-5 *}} dd + 20 * h 1 +20 * m 1 -5 * ee + ff) or ^{(aa-5 * bb + 20} * b + 20 * s 1 -5 * gg + hh)
j = Clip ((j ₁ +512) >> 10)

FIG. 5 is a diagram showing a 1/4 pixel generation method of the conventional processing procedure. Sub-pixels at positions a, c, d, e, f, g, i, k, n, p, q, and r are generated as 1/4 pixels. Note that the order of decimal pixels to be generated may be arbitrary. The calculation formula of ¼ pixel is as follows.
a = (G + b + 1) >> 1
c = (H + b + 1) >> 1
d = (G + h + 1) >> 1
n = (M + h + 1) >> 1
f = (b + j + 1) >> 1
i = (h + j + 1) >> 1
k = (j + m + 1) >> 1
q = (j + s + 1) >> 1
e = (b + h + 1) >> 1
g = (b + m + 1) >> 1
p = (h + s + 1) >> 1
r = (m + s + 1) >> 1

  In contrast to the conventional processing procedure described above, the reference image is H.264. The processing procedure of the present embodiment in the case of H.264 is as follows. FIG. 3 is a flowchart of a H.264 decimal pixel generation processing procedure. The reference image is H.264. Even in the case of H.264, as in the case of HEVC, first, a horizontal sub-pixel is generated (step S1), and then a vertical sub-pixel is generated (step S2). H. The decimal pixel generation circuit can be shared by making the order of decimal pixel generation the same in the case of H.264 and HEVC.

FIG. 7 shows H.264 in the embodiment of the present invention. It is a figure which shows a H.264 horizontal direction decimal pixel production | generation method. Sub-pixels at positions a, b, and c are generated as the sub-pixels in the horizontal direction. The calculation formula for the horizontal decimal pixels is as follows.
b ₁ = (E-5 ^* F + 20 ^* G + 20 ^* H-5 ^* I + J)
b = Clip ((b ₁ +16) >> 5)
a = (G + b + 1) >> 1
c = (H + b + 1) >> 1

FIG. 8 shows the H.264 in the embodiment of the present invention. 2 is a diagram illustrating a H.264 vertical-direction decimal pixel generation method. FIG. Sub-pixels at positions d, e, f, g, h, i , j, k, n, p, q, and r are generated as vertical sub-pixels. Note that the order of decimal pixels to be generated may be arbitrary. The formula for calculating the vertical fractional pixels is as follows.
h ₁ = (A-5 ^* C + 20 ^* G + 20 ^* M-5 ^* R + T)
h = Clip ((h ₁ +16) >> 5)
^{_{j 1 = (cc-5 *}} dd + 20 * h 1 +20 * m 1 -5 * ee + ff) or ^{(aa-5 * bb + 20} * b + 20 * s 1 -5 * gg + hh)
j = Clip ((j ₁ +512) >> 10)
d = (G + h + 1) >> 1
n = (M + h + 1) >> 1
f = (b + j + 1) >> 1
i = (h + j + 1) >> 1
k = (j + m + 1) >> 1
q = (j + s + 1) >> 1
e = (b + h + 1) >> 1
g = (b + m + 1) >> 1
p = (h + s + 1) >> 1
r = (m + s + 1) >> 1

  The reference image is H.264. The processing procedure (FIGS. 7 and 8) of this embodiment in the case of H.264 is different from the conventional processing procedure (FIGS. 4 and 5). However, the calculation formulas for generating decimal pixels at each position are the same.

  As described above, in the present embodiment, the filter coefficients of the horizontal filter 1 and the vertical filter 2 are dynamically changed, so that the H.V. H.264 can also be processed. As a result, HEVC and H.C. H.264 decimal pixel generation processing can be shared. Further, in the circuit according to the present embodiment shown in FIG. 1, the amount of hardware in the order of several tens of kilometers can be reduced as compared with the case where the conventional circuits shown in FIGS. 9 and 10 are simply merged.

1 horizontal filter, 2 vertical filter, 4, 5 coefficient selector

Claims (1)

A horizontal fractional pixel generation unit that inputs a reference image and generates a horizontal fractional pixel;
A vertical fractional pixel generator for generating a vertical fractional pixel by inputting the reference image and the horizontal fractional pixel;
A fractional pixel generator that performs processing for generating a fractional pixel from the reference image using a fractional pixel generation circuit including a coefficient selection unit that selects a filter coefficient of the horizontal direction fractional pixel generation unit and the vertical direction fractional pixel generation unit In the method
When the decimal pixel generation circuit generates a decimal pixel conforming to HEVC from the reference image, the coefficient selection unit includes first, -1,4, -11,40,40, -11,4, -1. Filter coefficient, −1, 4, −10, 58, 17, −5, 1, 0, and the decimal pixel generation circuit selects H.2 from the reference image. H.264 / AVC-compliant decimal pixels are generated, a third filter coefficient consisting of 1, -5, 20, 20, -5, 1, 0, 0, 0, 1, 1, 0, 0, 1, Select one of the fourth filter coefficients consisting of 1, 0,
When the decimal pixel generation circuit generates a decimal pixel based on HEVC from the reference image,
The horizontal sub-pixel generation unit, from the inputted reference image, to generate a horizontal ½ pixel based on the first filter coefficients from the inputted reference image, the second filter coefficients and generating all of the horizontal sub-pixel and generates a horizontal 1/4 pixel basis,
The vertical sub-pixel generation unit, from the horizontal sub-pixel and the inputted reference image, said first generates a vertical half-pixel based on the filter coefficient, wherein the input the reference image horizontal Generating a ¼ pixel in the vertical direction from the sub-pixel in the direction based on the second filter coefficient ,
The decimal pixel generation circuit generates H.264 from the reference image. When generating a fractional pixel conforming to H.264 / AVC,
The horizontal sub-pixel generation unit, from the inputted reference image, to generate a horizontal ½ pixel on the basis of the third filter coefficient, the generated and the inputted reference image horizontally 1 / Generating two horizontal pixels from two pixels based on the fourth filter coefficient to generate all the horizontal decimal pixels;
The vertical sub-pixel generation unit, from the horizontal sub-pixel and input the reference image, the third generates vertical half-pixel based on the filter coefficient, wherein the input the reference image horizontal from the vertical half-pixel and the generated direction decimal pixels, and a step of generating a vertical quarter-pixel on the basis of the fourth filter coefficient,
The horizontal fractional pixel is a fractional pixel in a horizontal direction with respect to an integer pixel;
The method for generating a fractional pixel, wherein the fractional pixel in the vertical direction is a fractional pixel in a direction perpendicular to the integer pixel and the fractional pixel in the horizontal direction.

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