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CA2084394A1 - Interconnexion multicouche supraconductrice formee d'un oxyde supraconducteur et sa methode de fabrication - Google Patents

Interconnexion multicouche supraconductrice formee d'un oxyde supraconducteur et sa methode de fabrication

Info

Publication number
CA2084394A1
CA2084394A1 CA2084394A CA2084394A CA2084394A1 CA 2084394 A1 CA2084394 A1 CA 2084394A1 CA 2084394 A CA2084394 A CA 2084394A CA 2084394 A CA2084394 A CA 2084394A CA 2084394 A1 CA2084394 A1 CA 2084394A1
Authority
CA
Canada
Prior art keywords
superconducting
current path
oxide superconductor
multilayer interconnection
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2084394A
Other languages
English (en)
Other versions
CA2084394C (fr
Inventor
Takao Nakamura
Hiroshi Inada
Michitomo Iiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP4328917A external-priority patent/JPH05251772A/ja
Application filed by Individual filed Critical Individual
Priority to CA002187113A priority Critical patent/CA2187113A1/fr
Publication of CA2084394A1 publication Critical patent/CA2084394A1/fr
Application granted granted Critical
Publication of CA2084394C publication Critical patent/CA2084394C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49888—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing superconducting material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/70—High TC, above 30 k, superconducting device, article, or structured stock
    • Y10S505/701—Coated or thin film device, i.e. active or passive
    • Y10S505/703—Microelectronic device with superconducting conduction line

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
CA002084394A 1991-12-02 1992-12-02 Interconnexion multicouche supraconductrice formee d'un oxyde supraconducteur et sa methode de fabrication Expired - Fee Related CA2084394C (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA002187113A CA2187113A1 (fr) 1991-12-02 1992-12-02 Interconnexion multicouche supraconductrice comportant un oxyde supraconducteur et methode de fabrication de cette interconnexion

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
JP34394091 1991-12-02
JP343940/1991 1991-12-02
JP347845/1991 1991-12-03
JP34784591 1991-12-03
JP350185/1991 1991-12-10
JP35018591 1991-12-10
JP4328917A JPH05251772A (ja) 1991-12-02 1992-11-13 超電導多層配線およびその作製方法
JP328917/1992 1992-11-13
JP328,917/1992 1992-11-13

Publications (2)

Publication Number Publication Date
CA2084394A1 true CA2084394A1 (fr) 1993-06-03
CA2084394C CA2084394C (fr) 1997-06-24

Family

ID=27480425

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002084394A Expired - Fee Related CA2084394C (fr) 1991-12-02 1992-12-02 Interconnexion multicouche supraconductrice formee d'un oxyde supraconducteur et sa methode de fabrication

Country Status (4)

Country Link
US (2) US5430012A (fr)
EP (1) EP0545811B1 (fr)
CA (1) CA2084394C (fr)
DE (1) DE69218895T2 (fr)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2084394C (fr) * 1991-12-02 1997-06-24 Takao Nakamura Interconnexion multicouche supraconductrice formee d'un oxyde supraconducteur et sa methode de fabrication
DE69328278T2 (de) * 1992-07-28 2000-11-30 Nippon Telegraph And Telephone Corp., Tokio/Tokyo Übergangsvorrichtung mit Gitteranpassung und Verfahren zu ihrer Herstellung
JPH08255938A (ja) * 1995-01-05 1996-10-01 Toshiba Corp 超電導配線と半導体装置
US5773875A (en) * 1996-02-23 1998-06-30 Trw Inc. High performance, low thermal loss, bi-temperature superconductive device
US5776863A (en) * 1996-07-08 1998-07-07 Trw Inc. In-situ fabrication of a superconductor hetero-epitaxial Josephson junction
SE9904263L (sv) * 1999-11-23 2001-05-24 Ericsson Telefon Ab L M Supraledande substratstruktur och ett förfarande för att producera en sådan struktur
US6420189B1 (en) 2001-04-27 2002-07-16 Advanced Micro Devices, Inc. Superconducting damascene interconnected for integrated circuit
US6482656B1 (en) 2001-06-04 2002-11-19 Advanced Micro Devices, Inc. Method of electrochemical formation of high Tc superconducting damascene interconnect for integrated circuit
US6635368B1 (en) 2001-12-20 2003-10-21 The United States Of America As Represented By The Secretary Of The Navy HTS film-based electronic device characterized by low ELF and white noise
JP4141407B2 (ja) * 2003-06-11 2008-08-27 株式会社リコー 半導体装置の製造方法
DE112005001495B4 (de) * 2004-06-24 2011-06-16 National Institute Of Advanced Industrial Science And Technology Supraleitendes Fehlerstrom-Begrenzungs-Element und Verfahren zur Herstellung desselben
US7533068B2 (en) 2004-12-23 2009-05-12 D-Wave Systems, Inc. Analog processor comprising quantum devices
CN101286544B (zh) * 2007-04-10 2013-01-30 中国科学院物理研究所 一种用于超导器件的超导多层膜及其制备方法
CA2719343C (fr) 2008-03-24 2017-03-21 Paul Bunyk Systemes, dispositifs et procedes de traitement analogique
US10468406B2 (en) 2014-10-08 2019-11-05 Northrop Grumman Systems Corporation Integrated enhancement mode and depletion mode device structure and method of making the same
EP3465558A4 (fr) 2016-06-07 2020-03-11 D-Wave Systems Inc. Systèmes et procédés pour topologie de processeur quantique
CN110050516B (zh) 2016-12-07 2023-06-02 D-波系统公司 超导印刷电路板相关的系统、方法和设备
US10936756B2 (en) 2017-01-20 2021-03-02 Northrop Grumman Systems Corporation Methodology for forming a resistive element in a superconducting structure
US11678433B2 (en) 2018-09-06 2023-06-13 D-Wave Systems Inc. Printed circuit board assembly for edge-coupling to an integrated circuit
US11647590B2 (en) 2019-06-18 2023-05-09 D-Wave Systems Inc. Systems and methods for etching of metals
US12033996B2 (en) 2019-09-23 2024-07-09 1372934 B.C. Ltd. Systems and methods for assembling processor systems
CN115497896A (zh) * 2022-08-31 2022-12-20 北京航天控制仪器研究所 一种带微流道封装基板及其制备方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4660061A (en) * 1983-12-19 1987-04-21 Sperry Corporation Intermediate normal metal layers in superconducting circuitry
US4689559A (en) * 1984-11-13 1987-08-25 Sperry Corporation Apparatus and method to reduce the thermal response of SQUID sensors
US4980338A (en) * 1987-11-16 1990-12-25 Semiconductor Energy Laboratory Co., Ltd. Method of producing superconducting ceramic patterns by etching
US5021867A (en) * 1989-05-30 1991-06-04 Westinghouse Electric Corp. Refractory resistors with etch stop for superconductor integrated circuits
JPH0355889A (ja) * 1989-07-25 1991-03-11 Furukawa Electric Co Ltd:The 超電導多層回路の製造方法
JPH03183207A (ja) * 1989-12-13 1991-08-09 Nissan Motor Co Ltd フィルタ回路
CA2038012A1 (fr) * 1990-03-14 1991-09-15 Hideki Shimizu Laminage de supraconducteurs en couches d'oxyde, et procede de fabrication connexe
EP0484252B1 (fr) * 1990-10-31 1996-03-20 Sumitomo Electric Industries, Ltd. Dispositif supraconducteur formé de matériau supraconducteur d'oxyde
CA2062294C (fr) * 1991-03-04 1997-01-14 Hiroshi Inada Couche mince de supraconducteur a orientations cristallines localement differentes et sa methode de fabrication
US5157466A (en) * 1991-03-19 1992-10-20 Conductus, Inc. Grain boundary junctions in high temperature superconductor films
CA2084394C (fr) * 1991-12-02 1997-06-24 Takao Nakamura Interconnexion multicouche supraconductrice formee d'un oxyde supraconducteur et sa methode de fabrication
CA2084556C (fr) * 1991-12-06 1996-12-24 So Tanaka Methode de fabrication de dispositifs a jonction de josephson a joint de grain artificiel

Also Published As

Publication number Publication date
DE69218895T2 (de) 1997-11-20
DE69218895D1 (de) 1997-05-15
US5430012A (en) 1995-07-04
US5811375A (en) 1998-09-22
EP0545811A3 (en) 1993-06-23
CA2084394C (fr) 1997-06-24
EP0545811B1 (fr) 1997-04-09
EP0545811A2 (fr) 1993-06-09

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