CA1260627A - Lithographic image size reduction photomask - Google Patents

Abstract

Disclosed is a process for reducing lithographic image size for integrated circuit manufacture. A mask of photosensitive material having an opening of a minimum size dictated by the limits of lithography is formed on a substrate. Reduction in the image size is achieved by establishing sidewalls to the interior vertical surfaces of the opening by depositing a conformal layer, followed by anisotropic etching. The dimension of the opening is reduced by the combined thickness of the two opposite insulator sidewalls.
In a specific direct application of the disclosed process, a photomask/stencil having a pattern of openings of a minimum size smaller than possible by lithography, per se, is formed.

Description

1260~Z~

LIT80GRAPHIC IMAGE SIZE REDUCTION ~o~s~

~ACKGROUND OF THE lNV~lON
The invention relates to a method of reducing lithographic image size for integrated circuit (IC) manufacture. More particularly, it is a method of forming a mask having openings of a size smaller than obtainable by litAograpny.
There has been an inexorable advance in IC
industry due to the insatiable appetite for scaling down the devices. Scaling device dimensions reduces cost of manufacture while increasing the performance (speed). While this advance can be attributed to new processing techniques such as replacement of wet etching by dry etching (plasma etching, reactive ion etching and ion milling), use of low-resistivity silicides and refractory metals as replacements for high-resistivity polysilicon interconnec~ions, multiple-~esists to compensate for wafer surface variations that thwart accurate fine-line lithography, laser and electron-beam processing to purify and red~ce defects in materials, nonoptical methods of inspecting line widths and layer-to-layer registration to replace optical methods incapable of measuring these parameters at low-micrometer levels, lithography

2~ has been the driving force behind each step forward.
Improved lithographic tools such as 1:1 optical projection systems fitted with deep-ultraviolet source a~nd optics, electron- beam, direct-step-on-wafer, and X-ray and ion-beam systems and improved photoresist materi~l Q and ~roc~^ses such as m~ltiIayer resist ~tili2ing a top resist sensitized to X-ray or elec-tron-beam and bottom straight optical resist layer(s) are some of the components of this driving force.
Despite this tremendous progress, there remains

3~ an ever-growing need for reduction of image sizes over and beyond that offered by enhancements to -` 1~6~

lithographic tools, materials and processes, per se.
~owever, the prior art has not been able to meet this need.
The invention precisely satisfies this need for reducing lithographic image sizes by extending litho-graphic resolution to smaller sizes than capable by lithography.

SUMMARY OF T~E lNv~LION
In its broadest form, the invention provides a method of reducing the size of a lithographic image by establishing a sidewall on the interior of the opening in the lithographic mask material used to obtain the image. In a specific embodiment, the invention presents a process for making a mask having openings of a size smaller than obtainable by lithography.
Starting with a substrate (e.g., semiconductor, insulator ~r metal~, a thin release layer of an insulator material, such as photoresist and silicon dioxide, is formed on the substrate. A thick layer of photosensitive material is then applied. The thick layer is patterned by lithographic means to have openings of a ;ni~.lm size dictated by limits of lithography. Thereafter, to further reduce the size of the openings, a conformal layer material is applied to the patterned photosensitive layer and the sub-strate portions ex~posed by the openings in the pat-terned layer. The thickness of the conformal layer material is determined by the desired reduction in the size of the openings. For example, for an elongated nrPn;ng~ the reduction in ~he width of the opening is ~ . Lely twice the thickness of the conformal layer. An example of the conformal layer material is SiXOy formed by plasma-deposited hexamethyldisilazane (HMDS). ~y directional reactive ion etchino (RIE), the conformal layer is removed from all the horizontal surfaces leaving sidewalls of the conformal layer ` ~ 2606Z7 material on the non-horizontal surfaces corresponding to the openings in the photosensitive material. The release layer exposed by the openings in the photo-sensitive material is also removed by RIE. The thick photosensitve mask in combination with the sidewalls of the conformal layer material constitute a new mask (stencil) having openings smaller than obtainable by iitn~gr~pny a;one. sinis new mask ~dll be useu for a variety of purposes including ion implantation to implant the substrate exposed by the reduced-di~ensioned openings therein, as a RIE mask to etch narrow trenches in the substrate, as an oxidation mask to form recessed oxide isolation in the exposed regions of the semiconductor substrate, as a contact or metallization mask to respectively establish narrow dimensioned contacts to or conductors on the sub-strate, etc. Following such use, the new mask is lifted off the substrate by subjecting the release layer to a wet etchant.
To form narrow and deep trenches in a semiconduc-tor substrate, the above mask forming process is modified by starting with a semiconductor substrate having thereon a thick insulator layer such as photo-resist or polyimide. The new mask as described above is formed on the thick insulator, after which the thick insulator layer is patterned by RIE using the new rlask as an RIE mask. Following the liftoff of the release layer, the patterned thick insulator layer on the s~bstrate will ser~e as a trench RIE mask for etching deep trenches having a width smaller than the lithog;-aphy limit in the semiconductor material.

~RIEF DESCRIPTION OF THE DRAWINGS
The novel features, process steps and their combination characteristic of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the detailed description which follows in conjunction with the accompanying drawings, wherein:
Figs. 1-4 are sequential cross-sectional repre-sentations of one embodiment of a process for forming a mask/stencil having opening(s) smaller than dictated by lithography limit.
~ig. 5 is s cross-sectional representation of an extension of the process step sequence illustrated in the preceding figures.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Now referring to the process steps illustrated in Figs. 1-4, the process is initiated starting with a substrate 10. The substrate 10 may be any material on which a photoactive layer can be coated and patterned by lithographic techniques. For example, the sub-strate 10 may be a semiconductor material, glass, i n~lll AtOr~ primary photosensitive material, metal or a combination thereof. Next, a release layer 12 is applied to the substrate 10. The release layer 12 is çomposed of a material that is easily removable from the substrate 10. Such removal is made by wet chemi-cal etchants or by oxygen ashing. Since the basic function of release layer 12 is to facilitate easy removal of itself, any subsequently formed layers-/structures thereon are correspondingly removed as well. E~amples of the material suitable for forming layer 12 include photoresist. In one example, AZ
1350J (trademark of American Hoechst Corporation) photoresist material is applied by spin coating, followed by baking at a temperatlure of about 200-250C
for about 30-60 mins. to obtain a release layer 12 of about 200-1000 A thickness- 8elow about 200 A thick-ness, the release layer ~ould be too thin to reliably coat the substrate 10.
Continuing with the present process, after forming the release layer 12, a thick imaging layer 14 1260627 G3~

of a photosensitive material is applied, for example, by spin-coating as illustrated in Fig. l. The imaging layer; 14 is of a sufficient thickness in the range 0.8-3 microns. An example of the material of layer 14 is AZ 1350J photoresist. After coating the photo-sensitive material, it is patterned in a desired pattern by pattern-exposing in a lithographic tool, developed, rinsed and drled For slmplic1ty or illustration, in Fig. l a single opening 16 having a lateral dimension A is shown in the layer 14 having a substantially horizontal surface 18 and substantially vertical surfaces 20-20. The dimension A may be the smallest image size that is obtainable by lithography.
In other words, the width A may be the smallest dimension that is achievable by pushing lithography (which includes x-ray, electron-beam, etc.) to its highest resolution limit. Next, the patterned photo-sensitive layer is subjected to a hardening process step to thermally stabilize the layer 14. Deep ultraviolet exposure or heat treatment at a tempera-ture of about 200-250C for about 1-2 mins. may be used for hardening. Another method of hardening the layer 14 is by subjecting it to a halogen gas plasma.
This hardening step is needed for conventional photo-resists, lest the photosensitive material constitut-ing layer 14 may bubble up, melt and flow or otherwise get degraded during the deposition of subsequent layers thereon.
The next step in the present process is estab-lishing sidewalls on the vertical surfaces 20-20 to reduce the lateral ~-m~ncion A of the opening 16 beyond that achievable by lithography alone. Sidewall technology is known to the prior art as exemplified by the following patents. U.S. pat. no. 4,209,349 assigned to the present assignee, ~tilizes sidewall technology for forming small openings in a mask.
According to this method, first insulator regions are ` --` 1260627 formed on a substrate so that horizontal and vertical surfaces are obtained. A second insulator layer is applied thereon of a material different from that of the first layer, and is subjected to RIE in such a manner that the horizontal regions of the second insulator are removed, with merely very narrow regions of this layer remaining on the vertical surface regions or the ~irst insulator, and the respective regions of the substrate, respectively. Subsequently, the exposed substrate regions are thermally oxidized, and for finally forming the desired mask openings the regions of the second insulator layer there are removed. U.S. pat. no. 3,358,340 describes a method of making submicron devices using sidewall image transfer. A conductive film of submicron thickness is deposited across a vertical step between adjacent surfaces of an isolation, and subsequently vertically etched until there remains only part of the conductive film which is adjacent to the vertical step. The L~ ~ining isolation not covered by the conductor is removed, thus obtaining a submicron-wide gate of an MOS field effect transistor. U.S. pat. nos. 4,419,809 and 4,419,810 assigned to the present assignee dis-close methods of making self-aligned field effect transistors using sidewall to define narrow gates.
U.S. pat. no. 4,462,846 discloses use of sidewalls to mi ni~ize birds beak extensions of recessed oxide isolation regions. U.S. pat. no. 4,502,914 assigned to the present assignee describes a method of making submicron structures by providing a polymeric material str~uc~ure having vertical walls, the latter serving to make sidewall structure of submicron width. The sidewall structures are directly used as masks. For negative lithography, another layer is applied over the sidewall structures, which is partly removed until the peaks of the sidewall structures are exposed.
Subsequently, the sidewall structures themselves are -- ~2606Z~
, .

removed and the resulting opening is used as a mask opening for fabricating integrated circuit devices.
To reduce the size of the opening 16 in the layer 14, referring to Fig. 2, a conformal layer 22 is formed over the patterned photosensitive layer 14 and the portion of the release layer 12 exposed by the opening 16 therein. The conformal layer material may be polysilicon, SiXOy, si;ic~n dioxiae, si;icvn nitride, silicon oxynitride or a combination thereof.
In general, the conformal layer 22 may be any material which can be deposited at a temperature low enough as to not cause degradation of the patterned photo-sensitive layer 14. A preferred material for forming layer 22 is SiXOy obtained by he~amethyldisilazane (HMDS) plasma deposition.
Typically, the layer 22 is formed by mounting the substrate with the structure of Fig. 1 in a plasma deposition system, introducing liguid ~MDS into the process chamber and generating the necessary electric field therein which transforms the liquid HMDS into a HMDS plasma. The HMDS plasma will deposit on the structure of Fig. l obtaining a conformal and uniform layer 22 of plasma-deposited HMDS having the composi-tion SiXOy. The thickness ~ of layer 22 is determined by the desired reduction in the lithographic image size in the photosensitive layer 14. Typically, for very large scale integrated circuit fabrication, the thickness of layer 22 is in the range 0.01 - 0.6 microns. The lower limit for the thickness of layer 22 is dictated by the requirements of good step coverage associated with the substantially vertical wall profile 20 in layer 14 and viability of the layer 22 as a thin film. The upper limit for the thickness of layer 22 is determined by the desired percentage reduction in the size of the opening 16 in the layer 14. The percentage reduction in the opening size is governed by the factor ?B/A. In other ~ords, if the --- 126(~627 size of the opening is 3 microns, in order to achieve a 66.6% reduction in the size of the hole 16 (or an actual reduction of the hole size to 1 micron), a 1 micron thick HMDS layer 22 is deposited. After forming the conformal layer 22, next by anisotropic etching it is removed from all the substantially horizontal surfaces leaving it only on the substan-tialiy ver~icai surraces or iayer 14. Rl~ may be accomplished by a halogen-containing etchant gas. One suitable etchant: gas is CF4. The resulting structure will be as shown in Fig. 3 where the unetched portions of layer 22 are designated by 24, now serving as side-walls on the vertical surfaces 20 of layer 14. Due to the establishment of the sidewalls 24 on the interior of the vertical surfaces of the opening, the size of the opening 16 is reduced to a new dimension designat-ed as C in Fig. 3. The relationship between the parameters A, B and C is given by: C = A - 2B.
Following the establishment of the sidewalls 24 on the vertical surfaces of the opening 16, the portion of the release layer 12 exposed by the reduced-size opening 16 is removed by RIE using, for example, either the same etchant species which facili-tated removal of layer 22 from the horizontal surfaces of layer 14 or 2 plasma.
The photosensitive mask in combination with the sidewalls 24 fabricated in this manner constitutes a new mask (or stencil) having openings of a substan-tially reduced dimension than obtainable by lithogra-phy alone. The new mask serves a variety of purposes.As illustrated in Fig. 4, for example, it may be used as an ion implantation mask to implant an extremely narrow/small region 26 of the substrate 10. Another application o the new mask is as an etch mask to etch extremely narrow deep/shallow trenches in the sub-strate 10. Yet another application is to grow a recessed isolation o~ide free of bird's beak and -` 1260627 bird's heàd of a width essentially equal to the dimension C by subjecting the substrate and the overlying stencil structure to a low temperature oxidation. A further use of the new mask is as a contact (liftoff) mask for establishing highly local-ized electrical contacts to the substrate. Another use of the mask is to form narrow conductor or insula-tor lines of widtn C on the substrate.
Once the intended use of the new mask is com-plete, it is removed from the substrate 10 by takingadvantage of the release layer 12. By subjecting the release layer 12 to a suitable etchant for example, a hot oxidizing acid such as nitric acid, sulphuric acid, or hot phenol it is lifted off the surface of lS the sùbstrate thereby removing the overlying layer 14 and its associated sidewalls 24. Alternatively, the photosensitive layer 14 and the release layer 12 may be removed concurrently by oxygen plasma. Any side-wall material 24 that remains is removed by mechanical means, CF4 plasma etch or washed off in a liquid base.
Turning to Fig. 5, there is shown in this figure an alternative process of fabricating a nonerodable stencil having openings therein of a size smaller than capable by lithography, per se. In this process, an underlayer 30 is formed between the substrate 10 and the release layer 12. (In this embodiment, the release layer 12 may be omitted.) The underlayer 30 - is substantlally thic~:er than the photosensitive material 14. For e~ample, when the substrate material is a semiconductor, the underlayer may be an insulator such as polyimide or photoresist_ After forming the sten~il precussor comprised of the release layer 12 and the photosensitive layer 14 having sidewalls 24 in the manner described above in conjunction with Figs.
1-4, the process is modified to anisotropically etch the underlayer 30 to transfer the opening 16 in the layer 14 to the underlayer 30 obtaining the opening 32 12606*7 c3i~

therein. When the underlayer is polyimide, this etching is done by using 02 plasma. Following the definition of the nonerodable mask 30, the overlying structure is removed by liftoff of the release layer as previously elaborated in conjunction with Fig. 4 description. The underlayer 30 defined in this manner will serve as a thick nonerodable mask for etching, ror eXampie; deep dnd extfemely narrow trenches in the substrate 10. One such trench is shown in Fig. 5 designated by ~umeral 34. The trench 34 will have near perfect vertical walls owing to the enormous thickness of the nonerodable mask.
Thus, there has been provided in accordance with the invention, a method of reducing lithographic image size that fully satisfies the objects and advantages set forth above. This method permits reduction in lithographic image si~e over and beyond that possible by improved lithographic resolution brought about by lithography tool enhancements. In other words, this method can be applied universally and for all time to come, to move lithographic image resolution a signifi-cant step ahead of improvements due to tool enhance-ments.
While the invention has been described in con-junction with preferred embodiments, it is evidentthat many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. It is, therefore, contemplated that the appended claims will embrace any such alternatives, modifications and variations as fall within the true scope and spirit of ~he inven-tion.

Claims (6)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A lithographic mask comprising:
a substrate, an underlayer formed on the substrate;
a release layer formed on the underlayer;
a radiation-sensitive imaging layer formed on the release layer and having at least one opening extending through the imaging layer, the opening having substantially vertical walls; and inorganic sidewalls of a common and uniform thickness formed on the interior surface of all of the substantially vertical walls, the bottom edge of the sidewalls being adjacent to the release layer, whereby the size of the opening is decreased to a size smaller than that obtainable by lithography;

the mask being suitable for use as an ion implantation mask, an etch mask, a contact mask, a mask for growing a recessed isolation oxide or a mask for forming narrow conductor or insulator lines.

2. The mask of claim 1 wherein the underlayer comprises polyimide or photoresist.

3. The mask of claim 1 wherein the underlayer is thicker than the imaging layer.

4. The mask of claim 1 wherein the underlayer is suitable for use as a non-erodable mask for etching deep and narrow trenches in the substrate.

5. A lithographic mask comprising:
a substrate of semiconductor material, glass, insulator material, photosensitive material or metal;
a polyimide underlayer formed directly on the substrate;
a photoresist release layer formed directly on the underlayer;
a hardened organic photoresist imaging layer formed directly on the release layer and having at least one opening extending through the imaging layer, the opening having substantially vertical walls; and sidewalls of polysilicon, SixOy, silicon dioxide, silicon nitride or silicon oxynitride, the sidewalls being of a common and uniform thickness formed directly on the interior surface of all of the substantially vertical walls, the bottom edge of the sidewalls being directly adjacent to the release layer, whereby the size of the opening is decreased to a size smaller than that obtainable by lithography;
the mask being configured for use as an ion implantation mask, an etch mask, a contact mask, a mask for growing a recessed isolation oxide or a mask for forming narrow conductor or insulator lines.

6. The mask of claim 5 wherein the underlayer is thicker than the imaging layer.