KR0172718B1 - Method of forming a semiconductor device - Google Patents
Method of forming a semiconductor device Download PDFInfo
- Publication number
- KR0172718B1 KR0172718B1 KR1019950012602A KR19950012602A KR0172718B1 KR 0172718 B1 KR0172718 B1 KR 0172718B1 KR 1019950012602 A KR1019950012602 A KR 1019950012602A KR 19950012602 A KR19950012602 A KR 19950012602A KR 0172718 B1 KR0172718 B1 KR 0172718B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- mask
- semiconductor device
- pattern
- width
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 11
- 238000002955 isolation Methods 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 239000002904 solvent Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000012938 design process Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000002209 hydrophobic effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Drying Of Semiconductors (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
Abstract
본 발명은 반도체 소자의 형성방법에 관한 것으로, 보다 구체적으로는 단차를 갖는 반도체 표면에 마스크 형성공정을 진행함에 있어서 발생하는 벌크 이펙트를 방지하고, 소자의 제조 수율을 향상시킬 수 있는 반도체 소자의 형성방법에 관한 것으로 반도체 소자의 형성방법에 있어서, 상부와 하부간의 두께차를 갖는 웨이퍼 상부에 패턴을 형성할 때, 두께차를 고려하여 패턴을 형성하기 위한 마스크 설계시 마스크의 단차에 따라 폭을 부분적으로 적절히 조절하여 패턴에 의한 식각 공정시 균일한 패턴을 이룸으로써, 디바이스 특성을 개선할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and more particularly, to forming a semiconductor device capable of preventing bulk effects generated in the process of forming a mask on a semiconductor surface having a step and improving the yield of manufacturing the device. In the method of forming a semiconductor device, when the pattern is formed on the wafer having a thickness difference between the top and bottom, the width is partially determined in accordance with the step of the mask in the mask design for forming the pattern in consideration of the thickness difference By properly adjusting to form a uniform pattern during the etching process by the pattern, it is possible to improve the device characteristics.
Description
제1도 (a)는 종래의 폴리 실리콘 배선을 형성하기 위한 포토 레지스터 마스크를 형성한 후의 단면도.1A is a cross-sectional view after forming a photoresist mask for forming a conventional polysilicon wiring.
(b)는 종래의 포토 레지스트 마스크를 형성한 후의 평면도.(b) is a top view after forming a conventional photoresist mask.
제2도는 본 발명의 실시예1에 따른 마스크 제작 평면도.2 is a plan view of manufacturing a mask according to the first embodiment of the present invention.
제3도는 본 발명의 실시예2에 따른 마스크 제작 평면도.3 is a plan view of manufacturing a mask according to the second embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 활성 영역 2 : 아이솔레이션 영역1: active area 2: isolation area
3 : 폴리 실리콘 4 : 포토 레지스트 패턴3: polysilicon 4: photoresist pattern
5 : 활성 영역상의 마스크 패턴 5' : 이이솔레이션상의 마스크 패턴5: mask pattern on active region 5 ': mask pattern on isolation
본 발명은 반도체 소자의 형성방법에 관한 것으로, 보다 구체적으로는 단차를 갖는 반도체 표면에 마스크 형성공정을 진행함에 있어서 발생하는 벌크 이펙트(bulk effect)을 방지하고, 소자의 제조 수율을 향상시켜 디바이스 특성을 개선시킬 수 있는 반도체 소자의 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and more particularly, to prevent bulk effects occurring during the process of forming a mask on a semiconductor surface having a step, and to improve device manufacturing yield to improve device characteristics. It relates to a method of forming a semiconductor device that can improve the.
일반적으로 반도체 소자의 제조에 있어서 포토 리소그래피(photo lithography)방법을 이용하여 웨이퍼의 표면에 집적회로의 패턴을 형성하는데, 그 방법은 다음과 같다.In general, in the manufacture of a semiconductor device using a photo lithography method to form a pattern of the integrated circuit on the surface of the wafer, the method is as follows.
우선, 웨이퍼의 표면을 세척하여 웨이퍼 표면의 미립자를 제거한 후, 포토 레지스트가 웨이퍼 표면에 잘 붙도록 하기위해 습기를 제거한다. 즉, 웨이퍼를 소수성 상태로 만든다. 또한, DCS 용제를 웨이퍼 표면에 도포하여 웨이퍼를 건조 상태로 만들어 접착성을 향상시킨다. 이와같은 상태에서 포토 레지스트를 스핀 코팅에 의한 방법으로 웨이퍼 표면에 코팅한다. 그 다음에 포토 레지스트의 용제를 증발시키는 열처리 공정인 소프트 베이킹 공정이 수행되는데, 용제를 증발시키는 이유는 용제가 포토 레지스트에 남아 있으면 폴리머의 노광에 의한 화학반응이 방해를 받으며, 또한 포토 레지스트를 웨이퍼 표면에 잘 붙게 하기 위함이다.First, the surface of the wafer is cleaned to remove particulates from the wafer surface, and then moisture is removed to ensure that the photoresist adheres well to the wafer surface. That is, the wafer is made hydrophobic. In addition, a DCS solvent is applied to the wafer surface to dry the wafer to improve adhesion. In this state, the photoresist is coated on the wafer surface by a spin coating method. Then, a soft baking process, which is a heat treatment process that evaporates the solvent of the photoresist, is performed. The reason for evaporating the solvent is that if the solvent remains in the photoresist, the chemical reaction by exposure of the polymer is interrupted, and the photoresist This is to adhere well to the surface.
이제 웨이퍼 표면에 코팅된 포토 레지스트에 패턴을 형성하기 위해 웨이퍼를 정확히 정렬시킨 다음, 노광시키는 공정이 수행된다. 이러한 노광공정에서 미세한 패턴을 형성하는데 있어서 주요 제한은 노출 방사원의 파장, 즉 마스크 주변에서의 빛의 회절각이며, 이 회절각에 의해 포토 레지스트의 패턴에 달라지게 된다. 일반적으로 노출광으로는 자외선을 사용한다.The process of aligning the wafers correctly and then exposing them is now performed to form a pattern in the photoresist coated on the wafer surface. The main limitation in forming a fine pattern in such an exposure process is the wavelength of the exposure radiation source, that is, the diffraction angle of light around the mask, and this diffraction angle changes the pattern of the photoresist. In general, ultraviolet light is used as the exposure light.
이러한 정렬 및 노광 공정 후에 설계된 마스크에 있던 패턴은 포토 레지스트에 옮겨지게 되는데, 이때 고분자화가 되지못한 부분도 존재하므로 화학약품으로 이를 제거하는 형상 공정이 수행된다.After the alignment and exposure process, the pattern in the designed mask is transferred to the photoresist. At this time, since there is a part that cannot be polymerized, a shape process of removing it with a chemical is performed.
그 다음에 식각, 포토 레지스트 제거, 확산 및 이온 주입, 증착, 금속 공정을 거쳐서 원하는 소자가 완성된다.The desired device is then completed through etching, photoresist removal, diffusion and ion implantation, deposition, and metal processing.
이러한 포토 리소그래피의 일련의 공정을 수행하여 반도체 소자의 일반적인 회로 형성하는데, 현재의 반도체 소자의 집적도가 현저히 증가함에 따라 소자를 형성하기 위한 막들이 연속적으로 적층을 이루게 되었고, 이로 인하여 하부 패턴에 의하여 상부 막의 토폴로지가 저하되어 패턴을 형성하는데 어려움이 있었다.A series of photolithography processes are performed to form a general circuit of a semiconductor device. As the degree of integration of a current semiconductor device increases significantly, films for forming a device are continuously stacked, and thus the upper part is formed by a lower pattern. The topology of the film was degraded, making it difficult to form a pattern.
종래의 굴곡부가 형성되어 있는 전체 구조 상부에 패턴을 형성하기 위하여, 예를들어 제1도(a) 및 (b)에 도시된 바와 같이, 기판면에 활성영역(1)간의 절연의 효과를 도모하기 아이솔레이션 영역(2) 즉, 필드 산화막을 형성한 다음, 필드 산화막이 형성된 전체 구조 상부에 폴리 실리콘(3)을 증착한다. 그 후, 상기 폴리 실리콘(3) 상부에 패턴 형성공정을 진행하기 위하여 포토 레지스트를 코팅하고, 경화한 다음 마스크 설계 공정시 형성된 소정의 레티클에 의해 노광하여 형성된 포토 레지스트 패턴(4)은 제1도 (a)에 도시된 바와 같이 하부에 이이솔레이션 영역(2)에 의해 토폴로지가 형성되어 있으므로, 상기 포토 레지스트 패턴(4)은 상기 아이솔레이션 영역(2) 상부의 포토 레지스트 패턴과 활성 영역(1)면에 형성된 포토 레지스트 패턴과 현저한 두께차를 갖게 되고, 이는 CD(critical dimension)의 차이를 발생하게 되여, 이로 인하여 프로화일에 변화를 주어 벌크 이펙트를 유발시키게 되어 제1도(b)에 도시된 바와 같이, 활성 영역 상부에는 원하는 폴리 실리콘(3) 배선 폭보다 넓게 구성되고, 필드 산화막 즉, 아이솔레이션 영역(2)에는 활성 영역(1) 상부의 폴리 실리콘(3) 배선폭보다 가늘게 형성되어 전체적으로 균일하지 못한 실리콘(3) 배선을 형성하게 된다.In order to form a pattern on the entire structure in which a conventional bent portion is formed, as shown in FIGS. 1A and 1B, for example, the effect of insulation between the active regions 1 on the substrate surface is achieved. The isolation region 2, that is, the field oxide film is formed, and then polysilicon 3 is deposited on the entire structure on which the field oxide film is formed. Thereafter, the photoresist pattern 4 formed by coating a photoresist on the polysilicon 3 to proceed with a pattern forming process, curing and exposing the photoresist with a predetermined reticle formed during the mask design process is shown in FIG. As shown in (a), the topology is formed by the isolation region 2 at the lower portion, so that the photoresist pattern 4 is formed on the photoresist pattern and the active region 1 above the isolation region 2. There is a remarkable thickness difference with the photoresist pattern formed on the surface, which causes a difference in CD (critical dimension), which causes the profile to be changed to cause a bulk effect, as shown in FIG. Similarly, the active region is formed wider than the desired polysilicon (3) wiring width, and the field oxide film, that is, the isolation region 2, is made of poly over the active region 1. Silicon 3 is formed thinner than the line width to form a not-uniform silicon (3) wiring as a whole.
따라서, 본 발명의 목적은 하부의 패턴에 의하여 굴곡부를 갖고 있어도, CD의 변화 없이 이펙트를 방지하여 균일한 배선을 형성할 수 있는 반도체 마스크 제작방법을 제공하는데 있다.Accordingly, it is an object of the present invention to provide a method for fabricating a semiconductor mask which can form a uniform wiring by preventing an effect without changing the CD even if the bottom portion has a bent portion.
상기한 본 발명의 목적을 달성하기 위하여 본 발명은 단차부를 구비한 웨이퍼 기판 상에 포토 레지스트막을 코팅하고, 마스크를 사용하여 노광하고, 현상하여 포토 레지스트 패턴을 구성하는 반도체 소자의 형성방법에 있어서, 상기 마스크는 설계 공정시 단차를 고려하여 마스크의 폭을 부분적으로 확대시키거나, 축소시킴으로써 균일한 배선을 이루는 것을 특징으로 한다.In order to achieve the object of the present invention described above, the present invention provides a method for forming a semiconductor device comprising a photoresist film coated on a wafer substrate having a stepped portion, exposed using a mask, and developed to form a photoresist pattern. The mask is characterized in that the uniform wiring by partially expanding or reducing the width of the mask in consideration of the step in the design process.
이한 첨부한 도면에 의거하여 본 발명을 자세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2도 및 제3도는 본 발명에 따른 반도체 마스크 제작방법을 나타낸 평면도이다.2 and 3 are plan views showing a method of fabricating a semiconductor mask according to the present invention.
[실시예 1]Example 1
먼저, 기준면상보다 높은 단차 영역의 마스크를 넓게 형성하는 방법으로 제2도에 도시된 바와 같이 활성 영역(1) 즉, 소자의 기본 전극이 구성되는 활성 영역(1)에는 크롬(마스크에 의해 노광시 빛이 차단되도록 형성하는 금속)을 형성하지 않고, 아이솔레이션 영역(2)에 크롬을 형성한 다음, 마스크를 형성하기 위한 설계공정시 단차의 두께 즉, 하부에 형성된 최상단의 막과 하단의 막의 두께차에 비례하여 아이솔레이션 영역(2)의 마스크 패턴(5')폭을 넓게 설계한다.First, as shown in FIG. 2, a method of forming a mask having a step height higher than a reference plane is wider, and as shown in FIG. Chromium is formed in the isolation region 2 without forming light when the light is blocked), and then the thickness of the step, that is, the thickness of the uppermost film and the lower film formed at the bottom, in the design process for forming the mask. The mask pattern 5 'width of the isolation region 2 is designed to be wider in proportion to the difference.
[실시예 2]Example 2
본 실시예는 낮은 단차를 갖는 영역의 마스크의 폭을 축소시키는 방법으로서, 예를들어 제3도에 도시된 바와 같이, 소자의 활성 영역(1)상의 마스크 패턴(5)은 아이솔레이션 영역(2)상의 마스크 패턴(5')보다 작은 폭으로 구성되고, 상기 폭을 감소하는 비율은 하부에 구성된 막들의 단차에 의해 조절하게 된다.The present embodiment is a method of reducing the width of a mask of a region having a low step height, for example, as shown in FIG. 3, the mask pattern 5 on the active region 1 of the device is isolated from the isolation region 2. It has a width smaller than the mask pattern 5 'on the top, and the ratio of decreasing the width is controlled by the step of the films formed below.
이상에서 상세히 설명한 바와 같이, 본 발명은 반도체 마스크를 제작하는 방법에 있어서, 상부와 하부간의 두께차를 갖는 하부 구조에 패턴을 형성할 때, 두께차를 고려하여 패턴을 형성하기 위한 마스크 설계시 마스크의 단차에 따라 폭을 부분적으로 적절히 조절하여 패턴에 의한 식각 공정시 균일한 패턴을 이룸으로써, 디바이스 특성을 개선할 수 있다.As described in detail above, in the method of manufacturing a semiconductor mask, when forming a pattern in the lower structure having a thickness difference between the upper and lower, the mask when designing the mask for forming the pattern in consideration of the thickness difference The device characteristics can be improved by forming a uniform pattern during the etching process by the pattern by partially adjusting the width in accordance with the step difference.
또한 본 발명은 활성 영역과 아이솔레이션 영역에 국한하지 않고, 패턴에 의해 단차가 존재하는 영역이면 균일하게 이용할 수 있으며, 마스크 설계시 마스크의 폭을 조절하여 균일한 배선을 형성하는 기술이면 본 발명에 모두 포함된다.In addition, the present invention is not limited to the active region and the isolation region, and may be used as long as there is a step difference due to the pattern. Included.
이상의 본 발명의 각종 다른 변형은 본 발명의 범위와 정신에 이탈함이 없이 기술에 숙련된 사람들에게는 명백하며, 즉시 만들어질수도 있다.Various other modifications of the invention described above are apparent to those skilled in the art without departing from the scope and spirit of the invention, and may be made immediately.
따라서, 이하에 첨부된 청구범위는 여기 설명한 것에 한정되는 것을 의도하는 것이 아니고, 오히려 그 청구범위는 이 발명이 속하는 당업자들에게 균등한 것으로 인정되는 모든 특징을 포함하는 것으로 해석된다.Accordingly, the claims appended hereto are not intended to be limited to those described herein, but rather, the claims are to be construed as including all features recognized as equivalent to those skilled in the art to which this invention belongs.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950012602A KR0172718B1 (en) | 1995-05-19 | 1995-05-19 | Method of forming a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950012602A KR0172718B1 (en) | 1995-05-19 | 1995-05-19 | Method of forming a semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960043030A KR960043030A (en) | 1996-12-21 |
| KR0172718B1 true KR0172718B1 (en) | 1999-03-30 |
Family
ID=19414950
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950012602A KR0172718B1 (en) | 1995-05-19 | 1995-05-19 | Method of forming a semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0172718B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100702114B1 (en) * | 2000-11-17 | 2007-03-30 | 주식회사 하이닉스반도체 | Solution of step difference of photoresist by exposure process |
-
1995
- 1995-05-19 KR KR1019950012602A patent/KR0172718B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR960043030A (en) | 1996-12-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100375908B1 (en) | Dry microlithography | |
| US20020064958A1 (en) | Exposure method | |
| KR100295426B1 (en) | Wiring forming method | |
| JPH10256394A (en) | Semiconductor structure and device | |
| US5922516A (en) | Bi-layer silylation process | |
| US5885756A (en) | Methods of patterning a semiconductor wafer having an active region and a peripheral region, and patterned wafers formed thereby | |
| JP5573306B2 (en) | Photomask blank manufacturing method | |
| KR0172718B1 (en) | Method of forming a semiconductor device | |
| JP3717348B2 (en) | Stencil mask manufacturing method | |
| US20070178409A1 (en) | Exposure method of forming three-dimensional lithographic pattern | |
| US20040092126A1 (en) | Method for preventing reworked photoresist from collapsing | |
| US6316340B1 (en) | Photolithographic process for preventing corner rounding | |
| US6686129B2 (en) | Partial photoresist etching | |
| EP0104235A4 (en) | Electron beam-optical hybrid lithographic resist process. | |
| JP2000277423A (en) | Manufacture of semiconductor device | |
| US5354706A (en) | Formation of uniform dimension conductive lines on a semiconductor wafer | |
| KR0179155B1 (en) | Method of manufacturing semiconductor device | |
| KR100807074B1 (en) | Manufacturing Method of Semiconductor Device | |
| KR20010027172A (en) | Method of forming patterns in semiconductor device | |
| US7892920B2 (en) | Method for manufacturing semiconductor device including implanting through a hole patterned from a first photoresist an oxide and a second photoresist | |
| JP3439488B2 (en) | Method for manufacturing semiconductor device | |
| KR950010853B1 (en) | Reverse contact manufacturing method of semiconductor device | |
| JPS6347924A (en) | Manufacture of semiconductor device | |
| KR0179339B1 (en) | Method of forming photoresist pattern | |
| KR100192369B1 (en) | Semiconductor device planarization method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19950519 |
|
| A201 | Request for examination | ||
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 19960401 Comment text: Request for Examination of Application Patent event code: PA02011R01I Patent event date: 19950519 Comment text: Patent Application |
|
| PG1501 | Laying open of application | ||
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 19981014 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 19981026 Patent event code: PR07011E01D |
|
| PR1002 | Payment of registration fee |
Payment date: 19981026 End annual number: 3 Start annual number: 1 |
|
| PG1601 | Publication of registration | ||
| PR1001 | Payment of annual fee |
Payment date: 20010918 Start annual number: 4 End annual number: 4 |
|
| PR1001 | Payment of annual fee |
Payment date: 20020918 Start annual number: 5 End annual number: 5 |
|
| PR1001 | Payment of annual fee |
Payment date: 20030919 Start annual number: 6 End annual number: 6 |
|
| PR1001 | Payment of annual fee |
Payment date: 20040920 Start annual number: 7 End annual number: 7 |
|
| PR1001 | Payment of annual fee |
Payment date: 20050922 Start annual number: 8 End annual number: 8 |
|
| PR1001 | Payment of annual fee |
Payment date: 20060920 Start annual number: 9 End annual number: 9 |
|
| PR1001 | Payment of annual fee |
Payment date: 20070914 Start annual number: 10 End annual number: 10 |
|
| FPAY | Annual fee payment |
Payment date: 20081006 Year of fee payment: 11 |
|
| PR1001 | Payment of annual fee |
Payment date: 20081006 Start annual number: 11 End annual number: 11 |
|
| LAPS | Lapse due to unpaid annual fee | ||
| PC1903 | Unpaid annual fee |
Termination category: Default of registration fee Termination date: 20100910 |