CA1213321A - Transistor inverter circuit - Google Patents

Abstract

Abstract A new and improved method and apparatus is dis-closed for inverting DC electrical power into AC elec-trical power by using a transistor inverter. A first transistor switching device is operatively coupled to an inductive load and to one potential from the DC power source. A first diode is operatively connected across and oppositely poled from the first transistor switching device. A second transistor switching circuit is opera-tively coupled to the inductive load and to the other potential of the DC power source. A second diode is operatively connected across and oppositely poled from the second transistor switching device. A capacitor is operatively coupled to the load and the other potential of the DC power source. The first transistor switching device is rendered conductive to couple the inductive load to the one potential of the DC source through the first transistor switching device while the second tran-sistor switching device is rendered non-conductive with a reverse bias potential. The first transistor switch-ing device is then rendered non-conductive with a re-verse bias potential and the load remains energized by the capacitor while the first transistor switching de-vice is turning off when a low voltage is across it.
The second transistor switching device is then rendered conductive after the voltage across the second transis-tor reaches a predermined value while the first transis-tor switching device is maintained non-conductive with a reverse bias potential. The load is coupled to the other potential of the DC power source through the sec-ond transistor switching device. The second transistor switching device is subsequently rendered non-conductive with a reverse bias potential and the load remains ener-gized by the capacitor while the second transistor switch-ing device is turning of f when a low voltage is across it . --

Description

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9-79 Descript:ion - Improved Transistor Inverter Circuit Technical Field r The present invention relates to a method and an apparatus for inverting DC electrical power into AC
electrical power for the purpose of driving an induc-tive load and is particularly directed to a transistor inverter circuit and a method for operating a transis-tor inver~er circuit to invert DC electrical power to single phase or polyphase AC electrical power capable of driving an inductive load where the voltaye level of the DC electrical power may be greater than ~he rated sustaining voltage or the rated collector-emitter block-ing voltage of the transistors.
Background Art Static inverters have been widely employed in the prior art to invert DC electrical power to single phase or polyphase AC electrical power. One class of static inverters for this purpose utilizes transistors to per-form the inversion by switching the DC power lines insequence to different AC output lines. The sequential switching operations performed by the transistors are controlled by logic circuits which supply electrical pulses to the base of the transistors to render them conductive or non-conductive. Upon being driven into conduction by a signal from a logic circuit, a transis-tor conducts for a fraction of a cycle of the desired output frequency of the AC output linesJ and is then turned of~.
Another class of static inverters utilize silicon controlled rectifiers (SCRs) for the purpose of per forming inversion of DC electrical power to AC electri-cal power. The sequential switching operations per-formed by the SCRs are also controlled by logic cir-cuits which control the supply of electrical pulses to L3~2~

a gate electrode of each SCR. Upon being gated into conduction by a pulse from a logic circuit, an SCR con-ducts for a fraction of a cycle of the desired output frequency of the AC output lines~ and then is turned o~f.
A problem with prior art inverters that utilize SCRs is the difficulty in turning the SCR off or ren-dering it non-conductive4 Prior art inverters turn off SCRs with the aid of commutating circuits which back-10 bias the cathode and anode electrodes of the SCR momen-tarily. The commutating circuits often employ auxil-lary SCRs and capacitors for turning off the main SCRs.
The use of transistors instead of SCRs eliminates the need for the use of a commutating circuit to shut the 15 switching device of. The conduction through the tran-sistor can be cut off by simply removing the command signal from the base of the transistor.
One problem with prior art inverters that utilize transistors as the switching devices is that transis-20 tors generally have a lower forward biased sustainingvoltage capability compared with SCRs. A transistor's voltage blocking capability is classified in~o a maximum collector to base voltage VCbO~ a maximum collector to emitter voltage VCeO and a maximum collector to emitter 25 sustaining voltage VCeo(sus). The Vceo(sus) f a tran-sistor is substantially less than the forward blocking ratings of an SCR. Therefore, if it was desired to invert large voltages, prior art inverters utilize 5CRs to perform the switching function.
Another problem with prior art inverters that util-ize ~ransistors as the switching devices is that tran-sistors bave a lower fault current capability as com-pared with SCRs. An SCR non-recurrent fault current handling capability is generally about 15 to 25 times 35 its continuous handling capability. Transistors can ~33~

handle non recurrent fault currents of only 2 to 3 times thei~ continuous current hand:Ling capability. However, this current handling capability disadvantage of transis-tors is often offset in transistor circuits by the abil-ity of the transistor to be turned of S to 50 timesfaster than an SCR and by a transistor's self current limiting characteristic.
In an attempt to so]ve the problem of lower tran-sistor sustaining voltage, the prior art has utilized snubber circuits in parallel across each switching tran-sistor. These snubber circuits include a diode and resistor connected in parallel which is in turn con-nected to a capacitor in series. The purpose of the snubber circuit is to shape the turn-on and turn-off load lines to maintain voltage levels within the safe operating range of the switching transistors. When a transistor is turned off, its associated snubber ca-pacitor is charged through the associated diode and the voltage across the transistor increases gradually. When the transistor is turned on, the associated resistor prevents a sudden discharge of the associated capacitor.
Although this configuration is useful in wave shaping, it does not provid~ a method or an apparatus tha~ would allow efficient operation of an inverter when the DC
bus voltage is sufficiently greater than a transistor's sustaining voltage rating. This is because the capaci-tor's stored energy must be dissipated in the resistor each time the transistor is turned on. Thus the capaci-tor must be kept small to avoid undesireably large los-ses and cannot perform sufficient load line shaping.Disclosure of the Invention The present invention provides a new and improved transistor inverter curcuit and a method for operating a transistor inverter curcuit that inverts DC electrical power into single phase or polyphase AC electrical power 3~32~

capable of driving an inductive load. The new method and apparatus in accordance with the present invention is designed to provide high voltage switching capabili- -ties without the need of SCRs and SCR commutation cir-cuits. The new method and apparatus is also designedto illiminate component failure of the switching tran-sistors in an inverter circuit which occurs when the level of this ~C voltage bus i5 significantly greater than the transistor's sustaining voltage rating.
1~ The method for energizing an inductive type load in accordance with the present invention comprises pro-viding a first energizing circuit for energizing the inductive load which includes a first transistor opera-tively connected to a DC energy bus, a first diode oper-atively coupled in parallel across and oppositely poled from the first transistor switching device and an energy storage means, the first energizing circuit operatively coupled to the load and a source of DC electrical energy.
A second energizing circuit is provided for energizing the inductive load which includes a second transistor switching device to couple DC electrical energy to the load and a second diode operatively coupled in parallel across and oppositely poled from the second transistor switching device. The first transistor switching de-vice is rendered conductive to energize the inductiveload while maintaining the second transistor switching device non conductive. The first transistor switching device is then rendered non-conductive and the energi-zation of the inductive load is continued by the energy ~
storage means. The energy storage means keeps the first transistor's collector to emitter voltage below its sustaining rating until it is completely non-conductive.
The second diode across the second transistor switching device provides energy to the inductive load when becom-ing forward biased. The second transistor switching :IL;2~33Zl device is rendered conductive to energize the inductiveload_while the first transistor switching device is mai~tained non-conductive. The signal that renders the ~
second transistor switching device conductive is not applied until a predetermined condition occurs.
A circuit for energizing an inductive load from a DC power source in accordance with the present inven-tion comprises a first transistor switching device oper-atively coupled to one potential of the DC power source and to the load. A first diode is operatively coupled in parallel across and oppositely poled from the first transistor switching device. A second transistor switch-ing device is operatively coupled to the other potential of the DC power source and to the load. A second diode is operatively coupled in parallel across and oppositely poled from the second transistor switching device. An energy storage means is operatively coupled to the load and to one DC source potential. This energy storage means is capable of limiting the rise of voltage poten-tial across the first or the second transistor switch-ing devices during transistor turn-off to ensure com-plete non-conductivity before maximum collector-emitter sustaining voltage is reached for such transistor. The energy storage means provides an alternate path for the load current during commutation. A base drive means is operatively coupled to the first transistor switching device and to the second transistor switching device.
The base drive means produces signals to selectively render the f irst and second transistor switching device 30 conductive or non-conductive. The signal that renders either transistor conductive is not applied until a predetermined condition occurs. The signal that renders either of the transistor s~itching devices non-conduc-tive preferably reverse biases such device. The load is energized through the conductive transistor.

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According to one aspect of the invention, time delay means is operatively coupled to the second transistor switching device and to the drive means for delaying the drive signal from the drive means to the second transistor switching device, the second transistor switching device being rendered conductive a predetermined amount of time after the first transistor switching device is rendered non-conductive.

According to another aspect of the invention, there is provided a time delay means operatively coupled to the first transistor switching device and to the drive means for delaying the drive signal from the drive means to the first transistor switching device, the first transistor switching device being rendered conductive a predetermined amount of time after the second transistor device is rendered non-eonduetive.

Bri f Description of the Drawings Figure 1 is a schematical representation of a transistor inverter circuit made in accordance with the present invention.
Figure 2 is a table showing the flring steps and conduction states of the inverter transistors of the present invention.
Figure 3 is a graphical representation of the line-to-neutral voltage across the A winding of the WYE-connected inductive load shown in Figure 1 as a function of the firing steps of the inverter circuit.
Figure 4 is a sehematical representation of a base drive circuit for a transistor made in accordance with the present invention.
Figures 5A-5E are graphical representations of voltage and eurrents of partieular eomponents of an inverter eircuit made in accordance with the present invention during a turn-off sequence.
Figure 6 is a sheematical representation of another embodiment of a base drive circuit made in accordanee with the present inventlon.

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Figure 7 is a schematical representation of still another embodiment of a base drive circuit made in accordance with the present invention.
Figure 8 is a schematical representation of yet another embodiment of a base drive circuit made in accordance with the present invention.

Best_Mode for Carryinq out the Invention Referring now to the drawings and more particularly to Figure 1, an inverter circuit 10 inverts DC electrical power from a variable voltage, DC power source ~' mab/ ~

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12 into three-phase AC electrical power which is util-ized to drive an inductive loa~ 14. The load 14 may take the form of a three-phase, AC motor. The three-phase inductive load 14 is shown as a WYE-connection with winding designations A, B and CO The junction oE
~he three windings N is the neutral of the WYE connec-tion. For the purposes of explanation, the DC buses are refered ~o as a positive bus and a negative bus.
Those skilled in the art will recognize that these are relative terms. It is to be understood that one of the buses is more negative than the other bus or that one of the buses is more positive than the other.
The two basic inverter circuits known in the art are the variable bus voltage inverter (W I) and the pulse width modulated inverter (PWM). The present in-vention is directed to a WI inverter. As mentioned, the purpose of a three-phase inverter is to invert a DC
electrical power into AC electrical power. This is accomplished by the use of six transistor switching devices grouped in three pairs and connected in a ser-ies across the DC power supply. Six different firing signals within the inverter circuit causes certain of the devices to become conductive or non-conductive which results in an output signal at the junction of the pairs to approximate a sinusoidal wave. The DC buses are coupled to the load through conductive transistor switch-ing devices. In the case of a VVI, the amplitude of each of the six steps is proportional to the voltage level of the DC power source.
~he inverter circuit 10 of the present invention includes a switching section 20 and a base drive and logic command circuit 22. The base drive and logic command circuit receives firing commands from a suit-able sour~e 24.

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The switching section 20 includes transistors Tl through T6 which are grouped into three series pairs, Tl and T4, T2 and T5, and T3 and T6, all of the series pairs are operatively connected in parallel across the output buses of the variable ~C power source 1~. Con-nections 16, 17 and 18 between the transistor pairs are operatively connected to phase A, B and C of the induc-tive load 14 respectively.
Diodes Dl through D6 are operatively connected in pairs across the supply 12 with one pair of diodes cor-responding with one pair of switchin~ transistors. Spe-cifically, diode Dl is operatively connected to junc-tion 16 and the positive bus and D4 is operatively con-nected to junction 16 and the negative bus. D2 and D5 are both connected to junction 17 and in series between the negative and positive busesO D3 and D6 are both connected to junction 18 and in series between the nega-tive and positive buses. All of the diodes are opposite-ly poled from their associated transistor.
The firing sequence of txansistors Tl -through T6 can be appreciated by referring to Figures 2 and 3.
full firing cycle includes six firing steps in which the three pairs of transistors are switched. The load is coupled to the DC buses through conductive ~ransis-tors. In step 1 of the firing sequence, transistors Tl, T3, and T5 are rendered conductive and transistors T2, T4 and T6 are rendered non-conductive. The poten-tial across the A-phase winding of the load 14 between the A input and the neutral N is graphically represented in Figure 3. In the second firing step, the transistors in the third transistor pair are switched. Transistor T3 is switched from conductive to non-conductive and transistor T6 is switched from non-conductive to conduc-tive while transistors Tl, T5 remain conductive. The 35 voltage across the A-phase winding of the inductive 12~33,;Z~

load 14 can be seen in step 2 of Figure 3. The third firi-ng step switches the conductive states of the second transistor pair T2 and T5 causing T2 to switch to conduc-tive and T5 to switch non-conductive. Step 4 switches the conductive states of Tl and T4, step 5 switches the conductive states of T3 and T6, and step 6 switches the conductive states of T2 and T5. The six step cycle is then repeated starting with step 1 which changes Tl from non-conductive to conductive and T4 from conductive to non-conductive. As those skilled in the art will appreciate, the six step firing sequence shown in Figure

2 yields a square, stepped wave shown in Figure 3. This square, stepped wave approximates a sinusoidal wave.
Continued sequencing of these steps of the table of Figure 2 will repeat the approximated sinusoidal output wave.
It is contemplated that the potential across the DC power source 12 can be as high as 600 volts to invert to a 460 volts AC outputO As those skilled in the art will appreciate, the potential across the non-conductive transistor of any given switching pair is equal to the potential across the source 12 since the other transis-tor in the pair is conductive. The maximum sustaining voltage for a transistor is typically below 600 volts.
A transistor is rated for three forward voltage poten-tials; (1) VCbol (2) VCeo~ and (3) Vceo (sus) The VCbO rating is the maximum collector to base voltage the transistor can handle. The VCeO is the maximum collector to emitter voltage the transistor can handle while nonconducting with the base open. The VCeO (sus) is the maximum voltage the transistor can handle while conducting significant currents and is also referred to as the sustaining voltage. When the transistor is re-verse biased, the VC20 rating is no longer descriptive of the operating condition and the transistor becomes ~2~3~3;Z~

capable Qf blocking a collector-emitter voltage equal to the VCbo rating. In a typlcal transistor, the VCbO
is much greater than the Vceo or Vceo (sus) For example, the VCbO Of a transistor may be 750 voltsl the VCeO 500 volts and the Vceo (sus) 350 volts- If a transistor is reversed biased when it is rendered non-conductive, the VCeO breakdown rating will increase and approach the VcbO rating. By using this principle, transistors can be used to switch large DC potentials from a source 12 if the transistors are first rendered non-conductive when a low voltage exists across its collector-emitter and the non-conductive transistors are reversed biased throughout their non-conductive mode.
Referring now to Figures 1 and 41 the present in-vention provides means for turning off the transistors at voltages below their Vceo (sus) rating~ and means for reverse biasing the switching transistors during their non-conductive mode to take advantage of their VCbO rating. Capacitors Cl, C2 and C3 are respectively connected to junctions 16, 17 and 18. The other end of capacitors Cl through C3 are operatively connected to one of the buses of the DC supply. These capacitors are non-dissipative snubbers. In the case of 2S capacitors Cl through C3, no energy is dissipated.
Rather, it is transferred between the capacitors and the load inductances. This approach allows a much larger capacitor to be used without increasing inverter losses. Thus the transistor load line may be freely altered to allow low loss switching well within the transistor's safe operating area.
The base drive and logic command circuit 22 in-cludes a logic command section 30 and a plurality of amplifiers 32, one for each transistor. As mentioned, the potential across the DC power source can be 600

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volts. Although one of the b~ses is referred to as the negative bus, the nomenclature i5 relative. If one considers the negative bus ground and the positive bus plus 600 VDC, another power supply with plus and minus voltage with respect to ground can be used to corltrol the conduction states of the transistors T4 through T6 since their emitters are connected to groundO By way of example, the emitter of transistor T4 is connected to ground. An amplifier 32 is operatively connected to another power source tha~ has a positive and negative 5 VDC potential with respect to the negative bus of the DC power source 12 and is operatively connected to the base of transistor T4. As those skilled in the art will appreciate, such an amplifier 32 can apply a drive signal to the base of a transistor T4 to render it con-ductive or can apply a reverse bias potential to the base of a transistor T4 to render it non-conductive.
The conduction states of transistors Tl through T3 are controlled by similar base drive circuits each having a separate positive and negative potential with respect to their emitters being used to apply a drive signal or a reverse bias signal to their bases.
During the switching of any particular transistor pair, a predetermined condition must occur prior to the completion o the switching sequence. The one transis-tor switching device of the pair that was conducting is first rendered non-conductive by a reverse bias signal from the drive circuit. The voltage across the transis-tor switched non-conductive is low at first because of the presence of the capacitor. This insures that the transistor has time to completely turn off before the voltage across it reaches its maximum rating level.
The predetermined condition that must exist before the transistor that was previously non-conductive is ren-dered conductive is tha~ the voltages across the transis-~%~.~3~

tors of the pair switching must reach predeterminedlevels. The occurrence of the predetermined condition can be sensed or it can be timed out taking circuit parameters into account. After a predetermined time delay elapses or the sensed voltage across one of the two transistors reaches a predetermined level, the pre-viously non-conducting transistor is rendered conduc-tive.
To better understand the invention, a speciic example is considered for switching from step one to step two in Figure 2. Prior to the switch, the initial conduction state of T3 in step one is conductive and T6 is non-conductiveO T6 during the non-conductive state is reversed biased by an amplifier to increase its col-lector to emitter breakdown voltage. The collector toemitter voltage across T6 when T3 is conducting is es-sentially the entire potential of the variable DC bus voltage since T3 is conductive. For example, if the DC
bus has a 600 volt potential, the collector to emitter voltage across transistor T6 will be 600 volts. From step one to step two transistor T3 is switched from conductive to a non-conductive state. The capacitor C3 continues energization of the load. T6 is switched from a non-conductive to a conductive state after a predetermined condition occurs.
The timing of the switching sequence will be better appreciated by referring to Figures 5A through 5E. Dur-ing the switch from step 1 to step 2 the transistor T3 is first turned off at time to, by the application of a reverse bias potential from an amplifier to the base of transistor T3. The reverse bias of T3 increases its collector to emitter breakdown voltage. The transistor T6 is maintained in a non-conductive state with a re-versed bias potential maintained on its base. The load winding current transfers from transistor T3 to capaci-:a2~33;~

tor C3 as soon as the transistor voltage begins to riseat time tl. Capacitor C3 charges at a rate determined by its capacitance and the magnitude of the winding current. At time t2, transitor T3 is completely non-conductive which occurs prior to the collector-emitter voltage across transistor T3 exceeding its sustaining voltage. The diode D6 prevents the potential at junc-tion 18 from falling more than one diode drop below the negative bus when it becomes forward biased at time t3.
Transistor T6 is then rendered conductive by an appli-cation of a drive potential on the base of transistor T6 from the base drive and logic command circuit 22 while T3 is maintained non-conductive by a reverse bias potential. Current continues to flow until the winding current decays to zero. Upon reversal, the transistor T6 carries the load current. The turn-on of transistor T6 always occurs while diode D6 is conducting.
Next, consider the switch from step four to step five in which T6 is switched non-conductive and T3 is switched conductive. First, T6 is switched non-conduc-tive by the application of a reverse bias potential on its base. Load current again transfers to the capaci-tor C3. The capacitor C3 keeps the transistor T6 col-lector-emitter voltage from rising above its VCeO (sus~
rating during the turn-off interval. The capacitor C3 then continues to charge to the opposite bus potential where the diode D3 prevents the potential at junction 18 from rising more than one diode drop above the posi-tive bus by taking over the load current from the capaci-tor. T3 is then rendered conductive by an applicationof a drive potential on the base of transistor T3 from the base drive and logic command circuit while T6 is maintained non-conductive by a reverse bias potential.
The timing for turning one transistor of a given pair off and the turning on of the other transistor is ~Z~3~

necessary to provide sufficient time to insure that the one transistor is turned off when the potential across such transistor is low and that the potential across the other transistor to be turned on is low prior to its turn-on. The occurrence of predetermined voltage levels of the transistors being switched can be insured by delaying the firing siynal a predetermined amount of time or by sensing voltage levels across the transistors.
The amount of the time delay can be readily calculated by one skilled in the art by considering all the circuit and load parameters.
Figure 6 shows one embodiment for delaying the firing signal from the logic command circuitry 30 for a predetermined amount of time by using a delay circuit 34 operatively connected between the logic command cir-cuit 30 and the amplifier 32. The logic command circuit 30 will generate a signal to render one of the transis-tors in the pair conductive contemperaneous with a sig-nal rendering the other transistor in the pair non-conductive. The signal to render the transistor con-ductive will be delayed a predetermined amount of time by the on-delay circuitry 34. After the predetermined time has lapsed, a signal will be generated to the ampli-fier 32 which in turn will render the transistor conduc-tive. The minimum amount of time that the signal mustbe delayed is a function of the bus voltage divided by the minimum current in the transistor at turn-off. For example, in the switching of transistors Tl and T4, the transistor Tl is to be rendered conductive when the voltage across it has reached a predetermined value.
The rate of charge of the capacitor can be easily cal-culated by taking into acount the parameters of the circuit and the parameters of the load 14. When tran-sistor T4 turns off, capacitor Cl begins to charge.
After a predetermined time delay which insures the vol-33~

tage across transistor Tl is Less than a predeterminedvalue, Tl i5 turned on. This time delay is a function of the capacitor and can be readily calculated~ 5ince load current does not flow in the transistor Tl until its polarity reverses, the maximum delay time is a func-tion of the load power factor. The time delay also insures that the transistor T4 i5 reversed biased and is completely off before the voltage across T4 exceeds its VCeo (sus) Figure 7 shows another embodiment of the present invention used to delay the conduction of one of the transistors of a given pair until a predetermined condi-tion is met which includes a sensor 36 operatively con-nected across the transistor that is operatively con-nected to the negative bus of the DC power supply 12.
The sensor 36 senses the voltage across the transistor with respect to its associated bus. Once the voltage has reached a predetermined value, the sensor 36 out-puts a signal which is ANDED by AND gate 38 with the logic command signal from the logic command circuitry 30. For example, the transistor T4 would not be acti-vated until the logic command signal is generated and the voltage across the tranSistQr is less than a prede termined value sensed by the sensor 36. A similar cir-cuit is also contemplated for transistor Tl and theremainder of the transistors in the inverter circuit.
Figure 8 shows yet another embodiment of the base drive circuitry used to conditionally control a driving signal which includes the sensor 36 which operates as described with reference to Figure 7. Also included in this embodiment is a current sensor 40 operatively con-nected between the emitter of a transistor and the nega-tive bus of the DC power source. The value o~ the cur-rent in the emitter leg is compared by a comparator 42 against a reference 44 to determine if the current in ~2~3~

the emitter leg is greater than a predetermined value.
The signal from the comparator 42 is ANDED with both the logic command signal from the logic circuitry 30 and the sensor signal from sensor 36 by an AND gate 46.
If the current in the emitter leg of the transistor is less than a predetermined value, the comparator 42 will allow the logic command signal and ~he sensor signal to pass through the AND gate 46. Those skilled in the art will appreciate that the current sensor 40, comparator 42 and reference signal 44 will function to deactivate the transis~or being driven if the current in the tran-sistor exceeds a predetermined value. This additional circuitry acts as a safety device to shut off the tran-sistor if a large amount of current is present through the transistor.
From the foregoing, it should be apparent that a new and improved method and apparatus for inverting DC
electrical power to AC electrical power using transistor switching devices has been provided. The new and im proved method includes providing a first energizing circuit for energizing the inductive load which in-cludes a first transistor switching device, a diode operatively coupled in parallel to and oppositely poled from the first transistor switch device in parallel and an energy storage means operatively coupled to an in-ductive load, providing a second energizing circuit for energizing the inductive load including a second tran-sistor switching device operatively coupled in parallel to and oppositely poled from the load and a second diode operatively coupled in parallel to and oppositely poled from the second transistor switching device in parallel, rendering the first transistor switching device conduc-tive to energize the inductive load while maintaining the second transistor switching device non-conductive, rendering the first transistor switching device non-~:~ 3L3~3~

conductive and continuing energization of the inductiveloa~ by the energy storage means, and, rendering the secQnd transistor switching device conductive after a predetermined conditio~ is met to energize the induc--tive load while maintaining the first transistor non-conductive~
The new and improved apparatus includes a first transistor and a first diode both operatively coupled in parallel and coupled between one potential of a DC
power source and to an inductive load, the first diode being oppositely poled from the first transistor, a second transistor and a second diode both operatively coupled in parallel and coupled between the other poten-tial of the DC power source and to the load, the second diode being oppositely poled from the second transistor, an energy storage means operatively coupled to the load, the energy storage means capable of continuing energiza-tion of the load and, a base drive means operatively coupled to the first transistor and the second transis-tor, the base drive means producing signals to selective-ly render the first and second transistors conductive or non-conductive/ the signal rendering either transis-tor non-conductive being a signal that reverse biases such transistor, the load being energized through a conductive transistor. The signal rendering such tran-sistor conductive is not applied until a predetermined condition occurs.
Possible modifications and variations of the inven-tion will be apparent to those skilled in the art from the foregoing detailed disclosure. Therefore, it is to be understood that within the scope of the appended claims the invention can be practiced otherwise than is specifically shown and described.

Claims (7)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A method for energizing an inductive type load comprising the steps of:
a) providing a first energizing circuit for coupling DC electrical energy to said inductive load, said first energizing circuit including a first transistor switching device, a first diode operatively coupled in parallel across and oppositely poled from said first transistor switching device, said first energizing circuit operatively coupled to said load and a source of DC electrical energy;
b) providing an energy storage means operatively coupled to said load and said DC electrical energy source;
c) providing a second energizing circuit for coupling DC electrical energy to said inductive load, said second energizing circuit including a second transistor switching and a second diode operatively coupled in parallel across and oppositely poled from said second transistor switching device;
d) rendering said first transistor switching device conductive to couple one side of said DC electrical energy to said inductive load while maintaining said second transistor switching device non-conductive;
e) rendering said first transistor switching device non-conductive and continuing energization of said inductive load by said energy storage means; and f) rendering said second transistor switching device conductive after a predetermined amount of time has elapsed after said first transistor switching device was rendered non-conductive to couple the other side of said DC
electrical energy to said inductive load while maintaining said first transistor switching device non-conductive.

2. The method of claim 1 further including the steps of:
g) rendering said second transistor switching device non-conductive and continuing energization of said inductive load by said energy storage means; and, h) rendering said first transistor switching device conductive after a predetermined amount of time has elapsed after said second transistor switching device was rendered non-conductive to couple said one side of said DC
electrical energy to said inductive load while maintaining said second transistor switching device non-conductive.

3. A method for switching power to an inductive load from a DC source having a first bus and a second bus, said first bus being more positive than said second bus, said method comprising the steps of:
a) providing a first transistor switching device operatively coupled to said load and said first bus and a first diode operatively coupled in parallel across and oppositely poled from said first transistor switching device;
b) providing a second transistor switching device operatively coupled to said load and said second bus and a second diode operatively coupled in parallel across and oppositely poled from said second transistor switching device;
c) providing an energy storage means operatively coupled to said load and to one of said buses;
d) providing a signal to said first transistor switching device to render it conductive while providing a reverse bias signal to said second transistor switching device to render it non-conductive, said load being operatively coupled to said first bus through said first transistor switching device;
e) providing a reverse bias signal to said first transistor switching device to render it non-conductive while maintaining said second transistor switching device non-conductive, energization of said load being sustained by said energy storage means; and, f) providing a signal to said second transistor switching device to render it conductive after a predetermined amount of time has elapsed after said first transistor switching device was rendered non-conductive, said load being operatively coupled to said second bus through said second transistor switching device.

4. The method of claim 3 further including the steps of:
g) providing a reverse bias signal to said second transistor switching device to render it non-conductive while maintaining said first transistor switching device non-conductive, energization of said load being sustained by said energy storage means; and, h) providing a signal to said first transistor switching device to render it conductive after a predetermiend amount of time has elapsed after said second transistor switching device was rendered non-conductive, said load being operatively coupled to said first bus through said first transistor switching device.

5. A method of controlling transistor switching devices in an inverter that supplies power to an AC inductive load from a DC source, said transistor switching devices oriented in pairs, one transistor of a pair being connected to the load and one potential of the DC source and the other transistor of such pair being connected to the load and the other potential of the DC source, and diodes, one each connected in parallel across and oppositely poled from each transistor switching device of such pair and a non-disippative snubber connected to the load and one of the DC potentials, said method comprising the steps of:
a) rendering one transistor switching device of a pair conductive with a drive potential and the other transistor switching device of such pair non-conductive, said load being energized through the conductive transistor switching device of such pair;
b) rendering said one transistor switching device of such pair non-conductive while sustaining energization of said load by said snubber; and c) rendering the other transistor switching device of the pair conductive with a drive potential after a predetermined time has elapsed after said one transistor switching device of such pair was rendered non-conductive, said load being energized through said other transistor of such pair.

6. A circuit for energizing an inductive load from a DC source having a first and a second bus, said first bus being more positive than said second bus, said circuit comprising:
a first transistor switching device operatively coupled to said first bus and to said load;
a second transistor switching device operatively coupled to said second bus and to said load;
an energy sustaining means operatively coupled to said load;
drive means operatively coupled to said first and second transistor switching devices for generating a drive signal to render said first transistor switching device conductive and a reverse bias signal to render said second transistor switching device non-conductive, said load being operatively coupled to said first bus through said first transistor switching device;
said drive means further generating a reverse bias signal to render said first transistor switching device non-conductive, energization of said load being sustained by said energy sustaining means;
said drive means yet further generating a drive signal to render said second transistor switching device conductive after a predetermined condition occurs, said load being operatively coupled to said second bus through said second transistor switching device; and time delay means operatively coupled to said second transistor switching device and to said drive means for delaying the drive signal from said drive means to said second transistor switching device, said second transistor switching device being rendered conductive a predetermined amount of time after said first transistor switching device is rendered non-conductive.

7. A circuit for energizing an inductive load from a DC source having a first and a second bus, said first bus being more positive than said second bus, said circuit comprising:

a first transistor switching device operatively coupled to said first bus and to said load;
a second transistor switching device operatively coupled to said second bus and to said load;
an energy sustaining means operatively coupled to said load;
drive means operatively coupled to said first and second transistor switching devices for generating a drive signal to render said first transistor switching device conductive and a reverse bias signal to render said second transistor switching device non-conductive, said load being operatively coupled to said first bus through said first transistor switching device;
said drive means further generating a reverse bias signal to render said first transistor switching device non-conductive, energization of said load being sustained by said energy sustaining means;
said drive means yet further generating a drive signal to render said second transistor switching device conductive after a predetermined condition occurs, said load being operatively coupled to said second bus through said second transistor switching device; and a time delay means operatively coupled to said first transistor switching device and to said drive means for delaying the drive signal from said drive means to said first transistor switching device, said first transistor switching device being rendered conductive a predetermined amount of time after said second transistor switching device is rendered non-conductive.