CA1048660A - Semiconductor on insulating substrate resistors and method of making the same - Google Patents
Semiconductor on insulating substrate resistors and method of making the sameInfo
- Publication number
- CA1048660A CA1048660A CA74215309A CA215309A CA1048660A CA 1048660 A CA1048660 A CA 1048660A CA 74215309 A CA74215309 A CA 74215309A CA 215309 A CA215309 A CA 215309A CA 1048660 A CA1048660 A CA 1048660A
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- Canada
- Prior art keywords
- layer
- region
- ions
- ion
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 239000000758 substrate Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 47
- 239000010703 silicon Substances 0.000 claims abstract description 47
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 45
- 238000005468 ion implantation Methods 0.000 claims abstract description 22
- 239000000370 acceptor Substances 0.000 claims abstract description 11
- 150000002500 ions Chemical class 0.000 claims description 43
- 229910052796 boron Inorganic materials 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000002513 implantation Methods 0.000 claims description 11
- -1 boron ions Chemical class 0.000 claims description 9
- 230000001133 acceleration Effects 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 7
- 239000011810 insulating material Substances 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 229910052594 sapphire Inorganic materials 0.000 claims description 5
- 239000010980 sapphire Substances 0.000 claims description 5
- 229910052596 spinel Inorganic materials 0.000 claims description 5
- 239000011029 spinel Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 4
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 238000005496 tempering Methods 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims 4
- 235000014786 phosphorus Nutrition 0.000 claims 4
- 239000002800 charge carrier Substances 0.000 description 6
- 230000037230 mobility Effects 0.000 description 2
- 150000003376 silicon Chemical class 0.000 description 2
- JUUBCHWRXWPFFH-UHFFFAOYSA-N Hydroxytyrosol Chemical compound OCCC1=CC=C(O)C(O)=C1 JUUBCHWRXWPFFH-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A B S T R A C T
A highly ohmic resistance is provided in a thin monocrystalline semiconductor layer on an electrically insulated substrate formed by pro-ducing a resistance channel in the layer in which acceptors and donors have been introduced by ion implantation. The silicon layer is covered by an insulating layer. Where the semiconductor layer is p-conducting, the re-sistance channel is arranged close to the boundary between the substrate and the semiconductor layer, the acceptors are introduced by ion implantations into the resistance channel, and the donors are introduced by a further ion implantation step into the region of the semiconductor layer above the res-istance channel. Where the silicon layer is n-conducting the resistance channel is located approximately in the middle of the semiconductor layer and acceptors are introduced into the zones beneath and above the resistance channel by means of ion implantation at various accelerating voltages.
A highly ohmic resistance is provided in a thin monocrystalline semiconductor layer on an electrically insulated substrate formed by pro-ducing a resistance channel in the layer in which acceptors and donors have been introduced by ion implantation. The silicon layer is covered by an insulating layer. Where the semiconductor layer is p-conducting, the re-sistance channel is arranged close to the boundary between the substrate and the semiconductor layer, the acceptors are introduced by ion implantations into the resistance channel, and the donors are introduced by a further ion implantation step into the region of the semiconductor layer above the res-istance channel. Where the silicon layer is n-conducting the resistance channel is located approximately in the middle of the semiconductor layer and acceptors are introduced into the zones beneath and above the resistance channel by means of ion implantation at various accelerating voltages.
Description
1~48660 The present invention relates to the field of high ohmic resistances formed in a semiconductor layer which may be conveniently used in integrated circuits, and particularly for use where static storage elements are required whose rest power loss is very low The highly ohmic resistance of the present invention comprises an electrically insulating substTate of a material such as spinel or sapphire upon which is formed a semiconductor layer of monocrystalline material such as silicon. Over the semiconductor layer there is formed an insulating layer such as silicon dioxide, Where the semiconductor layer is doped to be p-con-ducting, acceptors are introduced into the semiconductor layer by ion implan-tation to form a resistance channel. Donors are then introduced by further ion implantation into the region of the semiconductor layer above the res-; istance channel (i.e., below the insulating layer). Where the semiconductor layer is n-conducting, the resistance channel is formed approximately in the middle of the semiconductoT layer and acceptors are introduced into the ,~ regions beneath and above the resistance channel by ion implantation at var-ious accelerated voltages. The acceptors are preferably boron ions, and the donors are preferably phosphor ions.
Thus, in accordance with one aspect of the invention, there is " 20 provided an ohmic resistance comprising a substrate of insulating material, ~;
' a superimposed layer of semiconductor material of one impurity type, a layer of insulating material on said semiconductor layer, said semiconductor layer having a region with implanted ions therein of the same type as the conduct-,;. ~
~ ivity type of said semiconductor layer and having a second implanted ion re-. .
, gion in said semiconductor layer adjacent said insulating la~er, the ions ;; of said second region being of the opposite type to the conductivity type of said semiconductor layer, whereby said first ion implanted region provides a conducting resistance channel in said semiconductor layer.
In accordance with another aspect of the invention there is provided . .
a highly ohmic resistance comprising a monocrystalline silicon layer having ~. .
r"
. . ~ .
. . , . .
"' ' : .
1~48660 a resistance channel therein, said layer being formed on an electrically insulating substrate in whîch said silicon layer i5 an n conducting silicon layer, in which said resistance channel is arranged approximately in the middle of said layer~ in which acceptors are introduced into the zones beneath and above said resistance channel by means of ion implantation at different acceleration voltages.
According to another aspect of the invention there is provided the method of making a highly ohmic resistance in a semiconductor layer which includes forming a monocrystalline silicon layer on an insulating sub-strate, doping said silicon layer with an impurity of one impurity type, ~orming a layer of insulating material on said silicon layer, implanting ions in said silicon layer of a conductivity type corresponding to the impurity type of said silicon layer and in a region of said silicon layer spaced from said insulating layer, implanting ions in said silicon layer adjacent said insulating layer of the opposite conductivity type to the conductivity type of said silicon layer.
Figure 1 schematically illustrates a cross-section through a res-istance in accordance with the invention with a p-conducting silicon layer on an electrically insulating substrate.
Figure 2 illustrates the dependence of the charge carrier concen-tration upon the distcance from the surface of the silicon layer for the res-istance of the invention shown in Figure 1.
Figure 3 schematically illustrates a cross-section through a highly ohmic resistance in accordance with the invention with an n-conducting silicon ; layer on an electrically insulating substrate.
Figure 4 shows the dependence of the charge carrier concentration upon the distance from the surface of the silicon layer for the resistance of ; the invention shown in Figure 3.
, . .
, -la-. .
- :
- . ~ . :
1~48660 In Figure 1, the electrically insulating substrate, which pref-erably consists of spinel or sapphire, has formed thereon a p-conducting silicon layer 2. On this silicon layer 2 is arranged an electrically insul-ating layer 8, preferably a SiO2-layer.
- In association with the MOS technique, this layer 8 serves advan-tageously as gate insulator in the production of MOS field effect transist-ors on the same substrate.
In accordance with the invention, for the production of a high ohmic resistance in the lower part of the p-doped or non-dopet silicon layer
Thus, in accordance with one aspect of the invention, there is " 20 provided an ohmic resistance comprising a substrate of insulating material, ~;
' a superimposed layer of semiconductor material of one impurity type, a layer of insulating material on said semiconductor layer, said semiconductor layer having a region with implanted ions therein of the same type as the conduct-,;. ~
~ ivity type of said semiconductor layer and having a second implanted ion re-. .
, gion in said semiconductor layer adjacent said insulating la~er, the ions ;; of said second region being of the opposite type to the conductivity type of said semiconductor layer, whereby said first ion implanted region provides a conducting resistance channel in said semiconductor layer.
In accordance with another aspect of the invention there is provided . .
a highly ohmic resistance comprising a monocrystalline silicon layer having ~. .
r"
. . ~ .
. . , . .
"' ' : .
1~48660 a resistance channel therein, said layer being formed on an electrically insulating substrate in whîch said silicon layer i5 an n conducting silicon layer, in which said resistance channel is arranged approximately in the middle of said layer~ in which acceptors are introduced into the zones beneath and above said resistance channel by means of ion implantation at different acceleration voltages.
According to another aspect of the invention there is provided the method of making a highly ohmic resistance in a semiconductor layer which includes forming a monocrystalline silicon layer on an insulating sub-strate, doping said silicon layer with an impurity of one impurity type, ~orming a layer of insulating material on said silicon layer, implanting ions in said silicon layer of a conductivity type corresponding to the impurity type of said silicon layer and in a region of said silicon layer spaced from said insulating layer, implanting ions in said silicon layer adjacent said insulating layer of the opposite conductivity type to the conductivity type of said silicon layer.
Figure 1 schematically illustrates a cross-section through a res-istance in accordance with the invention with a p-conducting silicon layer on an electrically insulating substrate.
Figure 2 illustrates the dependence of the charge carrier concen-tration upon the distcance from the surface of the silicon layer for the res-istance of the invention shown in Figure 1.
Figure 3 schematically illustrates a cross-section through a highly ohmic resistance in accordance with the invention with an n-conducting silicon ; layer on an electrically insulating substrate.
Figure 4 shows the dependence of the charge carrier concentration upon the distance from the surface of the silicon layer for the resistance of ; the invention shown in Figure 3.
, . .
, -la-. .
- :
- . ~ . :
1~48660 In Figure 1, the electrically insulating substrate, which pref-erably consists of spinel or sapphire, has formed thereon a p-conducting silicon layer 2. On this silicon layer 2 is arranged an electrically insul-ating layer 8, preferably a SiO2-layer.
- In association with the MOS technique, this layer 8 serves advan-tageously as gate insulator in the production of MOS field effect transist-ors on the same substrate.
In accordance with the invention, for the production of a high ohmic resistance in the lower part of the p-doped or non-dopet silicon layer
2 by ion implantation, a p-conducting resistance channel 6 is produced in the vicinity of the boundary area between the insulating substrate 1 and the silicon layer 2. Preferably boron is implanted in the resistance chan-nel with the aid of ion implantation.
As the high density of crystal structural faults causes She mobil-ity of the charge carriers in ~he silicon layer to be low in the vicinity of the boundary between the silicon layer 2 and the substrate 1, only high resistance values are obtained even with relatively high implantation doses.
Thus as it is possible to impla~t relatively high doses, and since any I
ir ~
charges in the SiO2 influence the conductivity in the channel 6 only to a small extent, it is possible to produce resistances having stable character-istics and reproducible properties.
In order to preclude conductivity in the region 9 of the silicon layer 2 arranged above the resistance channel 6, by means of a second im-plantation step, the effective doping of ~he silicon layer in the region 9 ~ can be reduced so that on account of the normally prevailing positive sur-,i face charges in the SiO2 layer, this part of the layer is practically cleared of moving charge carriers and an n-conducting inversion layer is formed, which however, is insulated from the resistance channel by a pn-junction.
- Preferably, phosphorus ions are implanted in the upper region 9 of the layer 2 by an ion implantation step.
~' ~'' ' .
lr~a~8660 Advantageously, positive surface charges which exist at the bount-ary between the insulating substrate 1 and the silicon layer 2 have only a small influence on the resistance value of this resistance channel with the given doping of the resistance channel 6 of the silicon layer 2.
A specific example of a resistance in accordance with the embodi-ment of the invention as shown in Figure 1 will now be described. When the layer 2 has a thickness of 0.6 ~m and with a doping of approximately 3 x 1015 ` cm 3, and with an i~n implantation dose of approximately 1012cm 2 boron ions were implanted into the resistance channel 6. The thickness of the resis-tance channel 6 here amounted to 0.2 ~m. In the second ion implantation step ` phosphorus ions were implanted into the region 9 with an implantation dose of approximately 2 x lOllcm 2 The thickness of the region 9 was approximately 0.4 ~m.
Figure 2 illustrates the dependence of the effective concentration of the acceptors upon the distance from the boundary between the silicon dioxide layer and the silicon layer. As can be seen from this Figure, the concentration of the positive charge carriers is the greatest in the lower part 6 of the layer 2.
Tempering is preferably carried out after the ion implantation j 20 steps at a temperature of about 500C for a period of 5 to 15 minutes.
In Figure 3, the electrically insulating substrate which prefer-ably consists of spinel or sapphire is referenced 1. ~n the substrate 1 is arranged a silicon layer 21, and upon this silicon layer 21 is arranged an electrically insulating layer 81J preferably a layer of silicon dioxide. In the exemplary embodiment shown in Figure 3, the silicon layer 21 is n-conduct-ing. The n-conducting resistance channel 61 is arranged approximately in the middle of the layer 21. For the production of this channel, boron is implantet preferably with two implantation steps at different acceleration voltages aDd energies, in such manner that the maximum distribution is in the one case above and in the other case below the conductive resistance
As the high density of crystal structural faults causes She mobil-ity of the charge carriers in ~he silicon layer to be low in the vicinity of the boundary between the silicon layer 2 and the substrate 1, only high resistance values are obtained even with relatively high implantation doses.
Thus as it is possible to impla~t relatively high doses, and since any I
ir ~
charges in the SiO2 influence the conductivity in the channel 6 only to a small extent, it is possible to produce resistances having stable character-istics and reproducible properties.
In order to preclude conductivity in the region 9 of the silicon layer 2 arranged above the resistance channel 6, by means of a second im-plantation step, the effective doping of ~he silicon layer in the region 9 ~ can be reduced so that on account of the normally prevailing positive sur-,i face charges in the SiO2 layer, this part of the layer is practically cleared of moving charge carriers and an n-conducting inversion layer is formed, which however, is insulated from the resistance channel by a pn-junction.
- Preferably, phosphorus ions are implanted in the upper region 9 of the layer 2 by an ion implantation step.
~' ~'' ' .
lr~a~8660 Advantageously, positive surface charges which exist at the bount-ary between the insulating substrate 1 and the silicon layer 2 have only a small influence on the resistance value of this resistance channel with the given doping of the resistance channel 6 of the silicon layer 2.
A specific example of a resistance in accordance with the embodi-ment of the invention as shown in Figure 1 will now be described. When the layer 2 has a thickness of 0.6 ~m and with a doping of approximately 3 x 1015 ` cm 3, and with an i~n implantation dose of approximately 1012cm 2 boron ions were implanted into the resistance channel 6. The thickness of the resis-tance channel 6 here amounted to 0.2 ~m. In the second ion implantation step ` phosphorus ions were implanted into the region 9 with an implantation dose of approximately 2 x lOllcm 2 The thickness of the region 9 was approximately 0.4 ~m.
Figure 2 illustrates the dependence of the effective concentration of the acceptors upon the distance from the boundary between the silicon dioxide layer and the silicon layer. As can be seen from this Figure, the concentration of the positive charge carriers is the greatest in the lower part 6 of the layer 2.
Tempering is preferably carried out after the ion implantation j 20 steps at a temperature of about 500C for a period of 5 to 15 minutes.
In Figure 3, the electrically insulating substrate which prefer-ably consists of spinel or sapphire is referenced 1. ~n the substrate 1 is arranged a silicon layer 21, and upon this silicon layer 21 is arranged an electrically insulating layer 81J preferably a layer of silicon dioxide. In the exemplary embodiment shown in Figure 3, the silicon layer 21 is n-conduct-ing. The n-conducting resistance channel 61 is arranged approximately in the middle of the layer 21. For the production of this channel, boron is implantet preferably with two implantation steps at different acceleration voltages aDd energies, in such manner that the maximum distribution is in the one case above and in the other case below the conductive resistance
- 3 -., . :
.: -, - .
1~48tj60 channel 61. The doping of these two implanted p-conducting zones 91 and 71 are selected to be such that the positive surface charges at the two boundary areas inf}uence space charge in the zones 91 and 71 and thus can no longer influence the resistance. As, however, the mobility of the charge carriers is relatively high in the middle of the layer, the doping levels must be set with considerably more accuracy than in the case of the example in Figure 1.
Further details for the exemplary embodiment shown in Figure 3 will be given. Assuming a thickness of 0.8 ~m for the layer 21 and a doping of approximately 1016cm~3, in a first ion implantation step at an acceleration voltage of 150 KeV, boron ions are introduced into the zone 91 in an ion im-plantation dose of 2 x 1012cm~2. In a second implantation step, at an accel-eration voltage of 50 KeV, boron ions are introduced into the zone 71 in an implantation dose of 2 x lO12cm 2. The thickness of the zone 71 is 0.2 ~m and the thickness of the zone 91 is 0.2 ~m.
; With the resistances of the invention as illustrated in Figures 1 and 3, for the above-mentioned values, resistance values of approximately lo nto are obtained in the resistance channels. Here ~O is to be under-stood as the resistance of a square measured between two oppositely located sides.
~ 20 Expediently, tempering is carried out following the ion implant-; ation steps at a temperature of about 500C for a period of 5 to 15 minutes.
If only one resistance type is required in an integrated circuit, in particular in the case of a circuit with epitaxial silicon films on in-sulating layers, the design can be such that the resistance zones are not ; implanted until the circuit has been completed. This enables a multiple implantation of the resistance zones. With this measure the highly ohmic resistances can advantageously be set in accordance with the leakage currents occurring on a wafer or substrate so that by means of this adaptation of the ion implantation steps to the layer properties, above-average yields can ad-vantageously be achieved.
.~-, ,:
1~)4~660 ;
The resistance illustrated in Figure 1 can also be designed in such manner that in the case of an n-conducting silicon layer donors are in-troduced into the resistance channel by ion implantation ant that acceptors are introduced by ion implantation into the part lying above the resistanse : channel.
: The resistance shown in Figure 2 can be designed to be such that : with a p-conducting silicon layer donors are introduced into the zones above and below the resistance channel by ion implantation at various acceleration voltages.
.- 10 It will be apparent to those skilled in the art that many modif-ications and variations may be effected without departing from the spirit and scope of tho novel concepts of the present invention.
,' ':
.''' ' , .
.
.: -, - .
1~48tj60 channel 61. The doping of these two implanted p-conducting zones 91 and 71 are selected to be such that the positive surface charges at the two boundary areas inf}uence space charge in the zones 91 and 71 and thus can no longer influence the resistance. As, however, the mobility of the charge carriers is relatively high in the middle of the layer, the doping levels must be set with considerably more accuracy than in the case of the example in Figure 1.
Further details for the exemplary embodiment shown in Figure 3 will be given. Assuming a thickness of 0.8 ~m for the layer 21 and a doping of approximately 1016cm~3, in a first ion implantation step at an acceleration voltage of 150 KeV, boron ions are introduced into the zone 91 in an ion im-plantation dose of 2 x 1012cm~2. In a second implantation step, at an accel-eration voltage of 50 KeV, boron ions are introduced into the zone 71 in an implantation dose of 2 x lO12cm 2. The thickness of the zone 71 is 0.2 ~m and the thickness of the zone 91 is 0.2 ~m.
; With the resistances of the invention as illustrated in Figures 1 and 3, for the above-mentioned values, resistance values of approximately lo nto are obtained in the resistance channels. Here ~O is to be under-stood as the resistance of a square measured between two oppositely located sides.
~ 20 Expediently, tempering is carried out following the ion implant-; ation steps at a temperature of about 500C for a period of 5 to 15 minutes.
If only one resistance type is required in an integrated circuit, in particular in the case of a circuit with epitaxial silicon films on in-sulating layers, the design can be such that the resistance zones are not ; implanted until the circuit has been completed. This enables a multiple implantation of the resistance zones. With this measure the highly ohmic resistances can advantageously be set in accordance with the leakage currents occurring on a wafer or substrate so that by means of this adaptation of the ion implantation steps to the layer properties, above-average yields can ad-vantageously be achieved.
.~-, ,:
1~)4~660 ;
The resistance illustrated in Figure 1 can also be designed in such manner that in the case of an n-conducting silicon layer donors are in-troduced into the resistance channel by ion implantation ant that acceptors are introduced by ion implantation into the part lying above the resistanse : channel.
: The resistance shown in Figure 2 can be designed to be such that : with a p-conducting silicon layer donors are introduced into the zones above and below the resistance channel by ion implantation at various acceleration voltages.
.- 10 It will be apparent to those skilled in the art that many modif-ications and variations may be effected without departing from the spirit and scope of tho novel concepts of the present invention.
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.''' ' , .
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Claims (19)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. An ohmic resistance comprising a substrate of insulating material, a superimposed layer of semiconductor material of one impurity type, a layer of insulating material on said semiconductor layer, said semiconductor layer having a region with implanted ions therein of the same type as the conduct-ivity type of said semiconductor layer and having a second implanted ion re-gion in said semiconductor layer adjacent said insulating layer, the ions of said second region being of the opposite type to the conductivity type of said semiconductor layer, whereby said first ion implanted region provides a conducting resistance channel in said semiconductor layer.
2. An ohmic resistance as set forth in claim 1, which is further provided with a third implanted ion region between said first ion implanted region and said substrate, the ions of said third region being of the same type as the ions of said second region.
3. An ohmic resistance as set forth in claim 1, in which said semi-conductor layer is p-type silicon, the ions of said first implanted ion region are boron, and the ions of said second ion implanted region are phos-phorus.
4. An ohmic resistance as set forth in claim 1, in which said semi-conductor layer is n-type silicon, the ions of said first implanted ion re-gion are phosphorus and the ions of said second ion implanted region are boron.
5. An ohmic resistance as set forth in claim 2, in which the semi-conductor layer is n-type silicon, and in which the ions of said first im-planted ion region are phosphorus, the ions of said second and third implan-ted ion regions being boron.
6. An ohmic resistance as set forth in claim 2, in which the semicon-ductor layer is p-type silicon, and in which the ions of said first implanted ion region are boron, the ions of said second and third implanted ion regions being phosphorus.
7. An ohmic resistance as set forth in claim 1, in which said substrate is spinel.
8. An ohmic resistance as set forth in claim 1, in which said substrate is sapphire.
9. An ohmic resistance as set forth in claim 1, in which said insulat-ing layer is SiO2.
10. An ohmic resistance as set forth in claim 3, in which said semicon-ductor layer has a thickness of 0.6 µm and a doping of approximately 3 x 1015 cm-3, wherein the ion implantation dose of said first implanted ion region is approximately 1012cm-2 boron ions, and wherein the thickness of said resis-tance channel is approximately 0.2 µm, and wherein further the implantation dose of said second implanted ion region is approximately 2 x 1011cm-2, and wherein the thickness of said second ion implanted region is approximately 0.4 µm.
11. An ohmic resistance as set forth in claim 2, wherein the thickness of said semiconductor layer is approximately 0.8 µm with a doping of approx-imately 1016cm-3 and wherein said second implanted ion region has an implan-tation dose of 2 x 1012cm-2 of boron and wherein said third implanted ion region has an implantation dose of 2 x 1012cm-2.
12. A highly ohmic resistance comprising a monocrystalline silicon layer having a resistance channel therein, said layer being formed on an elec-trically insulating substrate in which said silicon layer is an n-conducting silicon layer, in which said resistance channel is arranged approximately in the middle of said layer, in which acceptors are introduced into the zones beneath and above said resistance channel by means of ion implantation at different acceleration voltages.
13. A highly ohmic resistance as set forth in claim 12, in which said substrate consists of spinel.
14. A highly ohmic resistance as set forth in claim 12, in which said substrate consists of sapphire.
15. A highly ohmic resistance as set forth in claim 12, in which said acceptors are boron ions.
16. The method of making a highly ohmic resistance in a semiconductor layer which includes forming a monocrystalline silicon layer on an insulating substrate, doping said silicon layer with an impurity of one impurity type, forming a layer of insulating material on said silicon layer, implanting ions in said silicon layer of a conductivity type corresponding to the impurity type of said silicon layer and in a region of said silicon layer spaced from said insulating layer, implanting ions in said silicon layer adjacent said insulating layer of the opposite conductivity type to the conductivity type of said silicon layer.
17. The method as set forth in claim 16, in which ions are implanted in a third region of said silicon layer between said first implanted region and said substrate, the ions of said third region being of the same type as the ions of said first region.
18. The method as set forth in claim 16, in which tempering is carried out following the ion implantation steps at a temperature of about 500°C
for a period of 5 to 15 minutes.
for a period of 5 to 15 minutes.
19. The method as set forth in claim 17, in which the ion implantation of said second implanted ion region is carried out at an acceleration voltage of 150 KeV and in which the implantation step of said third implanted ion region is carried out at an acceleration voltage of 50 KeV.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE2360962A DE2360962A1 (en) | 1973-12-06 | 1973-12-06 | HIGH RESISTANCE IN A THIN SINGLE CRYSTALLINE SILICONE LAYER |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1048660A true CA1048660A (en) | 1979-02-13 |
Family
ID=5900134
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA74215309A Expired CA1048660A (en) | 1973-12-06 | 1974-12-05 | Semiconductor on insulating substrate resistors and method of making the same |
Country Status (11)
| Country | Link |
|---|---|
| JP (1) | JPS5091291A (en) |
| AT (1) | AT342150B (en) |
| BE (1) | BE823055A (en) |
| CA (1) | CA1048660A (en) |
| CH (1) | CH580328A5 (en) |
| DE (1) | DE2360962A1 (en) |
| FR (1) | FR2254095A1 (en) |
| GB (1) | GB1474924A (en) |
| IT (1) | IT1026738B (en) |
| NL (1) | NL7415420A (en) |
| SE (1) | SE396498B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DD150415A3 (en) * | 1978-01-03 | 1981-09-02 | Guenter Weise | VOLTAGE-RELATED RESISTANCE |
-
1973
- 1973-12-06 DE DE2360962A patent/DE2360962A1/en active Pending
-
1974
- 1974-10-25 GB GB4637774A patent/GB1474924A/en not_active Expired
- 1974-11-14 AT AT912874A patent/AT342150B/en not_active IP Right Cessation
- 1974-11-26 NL NL7415420A patent/NL7415420A/en not_active Application Discontinuation
- 1974-12-03 IT IT30113/74A patent/IT1026738B/en active
- 1974-12-03 CH CH1599574A patent/CH580328A5/xx not_active IP Right Cessation
- 1974-12-05 CA CA74215309A patent/CA1048660A/en not_active Expired
- 1974-12-05 SE SE7415254A patent/SE396498B/en unknown
- 1974-12-05 FR FR7439812A patent/FR2254095A1/fr not_active Withdrawn
- 1974-12-06 JP JP49141093A patent/JPS5091291A/ja active Pending
- 1974-12-06 BE BE151249A patent/BE823055A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| SE7415254L (en) | 1975-06-09 |
| CH580328A5 (en) | 1976-09-30 |
| BE823055A (en) | 1975-04-01 |
| JPS5091291A (en) | 1975-07-21 |
| ATA912874A (en) | 1977-07-15 |
| AT342150B (en) | 1978-03-10 |
| GB1474924A (en) | 1977-05-25 |
| IT1026738B (en) | 1978-10-20 |
| SE396498B (en) | 1977-09-19 |
| NL7415420A (en) | 1975-06-10 |
| DE2360962A1 (en) | 1975-06-12 |
| FR2254095A1 (en) | 1975-07-04 |
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