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AU6843490A - Device for inserting information bits into a specific frame structure - Google Patents

Device for inserting information bits into a specific frame structure

Info

Publication number
AU6843490A
AU6843490A AU68434/90A AU6843490A AU6843490A AU 6843490 A AU6843490 A AU 6843490A AU 68434/90 A AU68434/90 A AU 68434/90A AU 6843490 A AU6843490 A AU 6843490A AU 6843490 A AU6843490 A AU 6843490A
Authority
AU
Australia
Prior art keywords
memory
binary elements
buffer
frame structure
information bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
AU68434/90A
Other versions
AU640727B2 (en
Inventor
Philippe Regent
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel CIT SA
Original Assignee
Alcatel CIT SA
Nokia Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel CIT SA, Nokia Inc filed Critical Alcatel CIT SA
Publication of AU6843490A publication Critical patent/AU6843490A/en
Application granted granted Critical
Publication of AU640727B2 publication Critical patent/AU640727B2/en
Anticipated expiration legal-status Critical
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/12—Arrangements providing for calling or supervisory signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Communication Control (AREA)
  • Mirrors, Picture Frames, Photograph Stands, And Related Fastening Devices (AREA)
  • Holo Graphy (AREA)
  • Television Systems (AREA)

Abstract

This device essentially comprises a so-called elastic memory, of specified capacity for holding, at each instant defined by a reduced insertion rate D2/n, binary elements constituting words read from a buffer-memory written to at a reduced rate D1/n, and which have not yet been inserted or have not yet been reinserted into the outgoing frames, and variable in number, dependent upon justifying commands generated earlier, means of selecting binary elements held in this elastic memory, for insertion or reinsertion into the outgoing frames, and means of temporarily freezing the buffer-memory reading clock when the number of binary elements to be stored in the elastic memory exceeds a predetermined limit fill value for this memory. <IMAGE>
AU68434/90A 1989-12-27 1990-12-21 Device for inserting information bits into a specific frame structure Expired AU640727B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8917256A FR2656479B1 (en) 1989-12-27 1989-12-27
FR8917256 1989-12-27

Publications (2)

Publication Number Publication Date
AU6843490A true AU6843490A (en) 1991-07-04
AU640727B2 AU640727B2 (en) 1993-09-02

Family

ID=9389013

Family Applications (1)

Application Number Title Priority Date Filing Date
AU68434/90A Expired AU640727B2 (en) 1989-12-27 1990-12-21 Device for inserting information bits into a specific frame structure

Country Status (8)

Country Link
EP (1) EP0435130B1 (en)
JP (1) JPH0761056B2 (en)
AT (1) ATE120909T1 (en)
AU (1) AU640727B2 (en)
CA (1) CA2033156C (en)
DE (1) DE69018411T2 (en)
ES (1) ES2071736T3 (en)
FR (1) FR2656479B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU634096B2 (en) * 1990-09-28 1993-02-11 Fujitsu Limited Sub-rate time switch

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2680062A1 (en) * 1991-07-31 1993-02-05 Cit Alcatel DEVICE FOR EXTRACTING BINARY INFORMATION ELEMENTS FROM A DETERMINED FRAME STRUCTURE.
ES2046106B1 (en) * 1992-02-18 1996-11-16 Estandard Electrica S A METHOD OF CARRYING OUT ALIGNING CIRCUITS IMMUNE TO THE SLIDES OCCURRED IN THE ELASTIC RECEPTION MEMORY.
FI90486C (en) * 1992-06-03 1999-08-11 Nokia Telecommunications Oy Method and apparatus for implementing elastic buffering in a synchronous digital communication system
FI90485C (en) * 1992-06-03 1999-08-11 Nokia Telecommunications Oy A method for disassembling and forming pointer frame structures
FI90484C (en) * 1992-06-03 1999-08-11 Nokia Telecommunications Oy Method and apparatus for monitoring the level of elastic buffer memory utilization in a synchronous digital communication system
US5327126A (en) * 1992-06-26 1994-07-05 Hewlett-Packard Company Apparatus for and method of parallel justifying and dejustifying data in accordance with a predetermined mapping
AU664097B2 (en) * 1992-06-26 1995-11-02 Hewlett-Packard Australia Limited A justifier and de-justifier

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2641488C2 (en) * 1976-09-15 1978-11-16 Siemens Ag, 1000 Berlin Und 8000 Muenchen Circuit arrangement for phase compensation in PCM exchanges
DE3600795A1 (en) * 1986-01-14 1987-07-16 Ant Nachrichtentech Digital communications system
JPH01123542A (en) * 1987-11-09 1989-05-16 Nec Corp Terminal station repeater
JPH0644746B2 (en) * 1988-03-25 1994-06-08 富士通株式会社 Parallel pulse insertion circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU634096B2 (en) * 1990-09-28 1993-02-11 Fujitsu Limited Sub-rate time switch

Also Published As

Publication number Publication date
JPH04211535A (en) 1992-08-03
DE69018411T2 (en) 1995-08-03
AU640727B2 (en) 1993-09-02
CA2033156A1 (en) 1991-06-28
ES2071736T3 (en) 1995-07-01
DE69018411D1 (en) 1995-05-11
JPH0761056B2 (en) 1995-06-28
ATE120909T1 (en) 1995-04-15
CA2033156C (en) 1994-08-16
EP0435130B1 (en) 1995-04-05
FR2656479A1 (en) 1991-06-28
FR2656479B1 (en) 1994-04-08
EP0435130A1 (en) 1991-07-03

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