AU507254B2 - Double phase locked loop receiver - Google Patents
Double phase locked loop receiverInfo
- Publication number
- AU507254B2 AU507254B2 AU19763/76A AU1976376A AU507254B2 AU 507254 B2 AU507254 B2 AU 507254B2 AU 19763/76 A AU19763/76 A AU 19763/76A AU 1976376 A AU1976376 A AU 1976376A AU 507254 B2 AU507254 B2 AU 507254B2
- Authority
- AU
- Australia
- Prior art keywords
- locked loop
- phase locked
- double phase
- loop receiver
- receiver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/14—Demodulator circuits; Receiver circuits
- H04L27/144—Demodulator circuits; Receiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements
- H04L27/152—Demodulator circuits; Receiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements using controlled oscillators, e.g. PLL arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/14—Demodulator circuits; Receiver circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NLNL7513610 | 1975-11-21 | ||
NL7513610A NL7513610A (nl) | 1975-11-21 | 1975-11-21 | Ontvanger voor synchrone signalen met dubbele fasevergrendelde lus. |
Publications (2)
Publication Number | Publication Date |
---|---|
AU1976376A AU1976376A (en) | 1978-05-25 |
AU507254B2 true AU507254B2 (en) | 1980-02-07 |
Family
ID=19824895
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU19763/76A Expired AU507254B2 (en) | 1975-11-21 | 1976-11-18 | Double phase locked loop receiver |
Country Status (8)
Country | Link |
---|---|
JP (1) | JPS5264260A (fr) |
AU (1) | AU507254B2 (fr) |
CA (1) | CA1066782A (fr) |
DE (1) | DE2651043C3 (fr) |
FR (1) | FR2332660A1 (fr) |
GB (1) | GB1507638A (fr) |
NL (1) | NL7513610A (fr) |
SE (1) | SE410693B (fr) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2823343B1 (de) * | 1978-05-29 | 1979-08-16 | Siemens Ag | Verfahren und Anordnung zur Taktsignalrueckgewinnung bei digitaler Signaluebertragung |
FR2441298A1 (fr) * | 1978-11-07 | 1980-06-06 | Cit Alcatel | Dispositif de recuperation de rythme |
JPS55165648A (en) * | 1979-06-12 | 1980-12-24 | Nec Corp | Method of sorting and inspecting semiconductor device |
ZA805414B (en) * | 1979-09-14 | 1981-08-26 | Plessey Overseas | Arrangements for data timing recovery from distorted signals for use in adaptive modems with multi-level coding |
JP2804755B2 (ja) * | 1986-09-01 | 1998-09-30 | 株式会社日立製作所 | Fsk信号復調回路 |
CN107037487B (zh) * | 2016-02-04 | 2023-06-20 | 中国石油化工集团有限公司 | 一种井间电磁同步测量系统 |
-
1975
- 1975-11-21 NL NL7513610A patent/NL7513610A/xx not_active Application Discontinuation
-
1976
- 1976-11-09 DE DE2651043A patent/DE2651043C3/de not_active Expired
- 1976-11-18 CA CA266,007A patent/CA1066782A/fr not_active Expired
- 1976-11-18 SE SE7612875A patent/SE410693B/xx unknown
- 1976-11-18 JP JP51137862A patent/JPS5264260A/ja active Pending
- 1976-11-18 GB GB48091/76A patent/GB1507638A/en not_active Expired
- 1976-11-18 AU AU19763/76A patent/AU507254B2/en not_active Expired
- 1976-11-19 FR FR7634924A patent/FR2332660A1/fr active Pending
Also Published As
Publication number | Publication date |
---|---|
GB1507638A (en) | 1978-04-19 |
DE2651043A1 (de) | 1977-05-26 |
JPS5264260A (en) | 1977-05-27 |
AU1976376A (en) | 1978-05-25 |
SE410693B (sv) | 1979-10-22 |
SE7612875L (sv) | 1977-05-22 |
DE2651043C3 (de) | 1981-07-30 |
FR2332660A1 (fr) | 1977-06-17 |
DE2651043B2 (de) | 1980-09-11 |
NL7513610A (nl) | 1977-05-24 |
CA1066782A (fr) | 1979-11-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
AU503854B2 (en) | Phase-locked loop phase detector | |
AU502220B2 (en) | Receiver tuning | |
AU502221B2 (en) | Receiver tuning | |
CA1012619A (en) | Drift compensated phase lock loop | |
AU510605B2 (en) | Phase locked loop | |
ZA76644B (en) | Wideband phase locked loop transmitter system | |
AU503350B2 (en) | Digital phase discriminator | |
AU539894B2 (en) | Double phase locked loop | |
AU470507B2 (en) | Phase locked loop | |
AU541683B2 (en) | Phase locked loop | |
JPS52122409A (en) | Phase locked loop transmitter*receiver | |
AU512493B2 (en) | Receiver tuning | |
AU506625B2 (en) | Phase locked loop circuit | |
CA1021411A (fr) | Boucle a blocage de phase | |
AU507254B2 (en) | Double phase locked loop receiver | |
CA1014625A (en) | Phase lock loop circuit | |
JPS525247A (en) | Phase locked loop device | |
AU500955B2 (en) | Phase-locked loop | |
AU502525B2 (en) | Receiver tuning | |
AU1011376A (en) | Receiver tuning | |
AU515112B2 (en) | Phase locked loop | |
AU508442B2 (en) | Receiver tuning | |
JPS5374307A (en) | Phase synchronization tuning receiver | |
AU481558B2 (en) | Phase locked loop transmitter | |
CA903322A (en) | Digital phase locked loop |