ATE373876T1 - Verbessertes layout einer sram-speicherzelle - Google Patents

Verbessertes layout einer sram-speicherzelle

Info

Publication number: ATE373876T1
Authority: AT; Austria
Prior art keywords: memory cell; conductivity type; inverters; transistor; switches
Prior art date: 2004-04-01

Application number

AT05718464T

Other languages

English (en)

Inventor

Cedric Mayor

Denis Dufourt

Original Assignee

Soisic

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2004-04-01

Filing date

2005-03-25

Publication date

2007-10-15

2005-03-25 Application filed by Soisic filed Critical Soisic

2007-10-15 Application granted granted Critical

2007-10-15 Publication of ATE373876T1 publication Critical patent/ATE373876T1/de

Classifications

- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices

Landscapes

Semiconductor Memories (AREA)
Static Random-Access Memory (AREA)

AT05718464T 2004-04-01 2005-03-25 Verbessertes layout einer sram-speicherzelle ATE373876T1 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
US55916704P	2004-04-01	2004-04-01

Publications (1)

Publication Number	Publication Date
ATE373876T1 true ATE373876T1 (de)	2007-10-15

Family

ID=34964577

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
AT05718464T ATE373876T1 (de)	2004-04-01	2005-03-25	Verbessertes layout einer sram-speicherzelle

Country Status (6)

Country	Link
US (1)	US7706172B2 (de)
EP (1)	EP1730777B1 (de)
JP (1)	JP5149617B2 (de)
AT (1)	ATE373876T1 (de)
DE (1)	DE602005002546T2 (de)
WO (1)	WO2005096381A1 (de)

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US8653857B2 (en)	2006-03-09	2014-02-18	Tela Innovations, Inc.	Circuitry and layouts for XOR and XNOR logic
US9230910B2 (en)	2006-03-09	2016-01-05	Tela Innovations, Inc.	Oversized contacts and vias in layout defined by linearly constrained topology
US9009641B2 (en)	2006-03-09	2015-04-14	Tela Innovations, Inc.	Circuits with linear finfet structures
US8839175B2 (en)	2006-03-09	2014-09-16	Tela Innovations, Inc.	Scalable meta-data objects
US7956421B2 (en)	2008-03-13	2011-06-07	Tela Innovations, Inc.	Cross-coupled transistor layouts in restricted gate level layout architecture
US8658542B2 (en)	2006-03-09	2014-02-25	Tela Innovations, Inc.	Coarse grid design methods and structures
US7908578B2 (en)	2007-08-02	2011-03-15	Tela Innovations, Inc.	Methods for designing semiconductor device with dynamic array section
US7446352B2 (en)	2006-03-09	2008-11-04	Tela Innovations, Inc.	Dynamic array architecture
US8448102B2 (en)	2006-03-09	2013-05-21	Tela Innovations, Inc.	Optimizing layout of irregular structures in regular layout context
US9035359B2 (en)	2006-03-09	2015-05-19	Tela Innovations, Inc.	Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US9563733B2 (en)	2009-05-06	2017-02-07	Tela Innovations, Inc.	Cell circuit and layout with linear finfet structures
US7763534B2 (en)	2007-10-26	2010-07-27	Tela Innovations, Inc.	Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8541879B2 (en)	2007-12-13	2013-09-24	Tela Innovations, Inc.	Super-self-aligned contacts and method for making the same
US8667443B2 (en)	2007-03-05	2014-03-04	Tela Innovations, Inc.	Integrated circuit cell library for multiple patterning
US8453094B2 (en)	2008-01-31	2013-05-28	Tela Innovations, Inc.	Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en)	2008-03-27	2011-05-10	Tela Innovations, Inc.	Methods for multi-wire routing and apparatus implementing same
EP2321748B1 (de)	2008-07-16	2017-10-04	Tela Innovations, Inc.	Zellsynchronisierungs- und positionierungsverfahren in einer dynamischen feldarchitektur und umsetzung des verfahrens
US9122832B2 (en)	2008-08-01	2015-09-01	Tela Innovations, Inc.	Methods for controlling microloading variation in semiconductor wafer layout and fabrication
JP5364108B2 (ja) *	2009-01-19	2013-12-11	株式会社日立製作所	半導体装置の製造方法
SG165252A1 (en)	2009-03-25	2010-10-28	Unisantis Electronics Jp Ltd	Semiconductor device and production method therefor
JP5032532B2 (ja) *	2009-06-05	2012-09-26	ユニサンティスエレクトロニクスシンガポールプライベートリミテッド	半導体装置及びその製造方法
JP5006378B2 (ja)	2009-08-11	2012-08-22	ユニサンティスエレクトロニクスシンガポールプライベートリミテッド	半導体装置及びその製造方法
JP5006379B2 (ja) *	2009-09-16	2012-08-22	ユニサンティスエレクトロニクスシンガポールプライベートリミテッド	半導体装置
US8661392B2 (en)	2009-10-13	2014-02-25	Tela Innovations, Inc.	Methods for cell boundary encroachment and layouts implementing the Same
FR2956516B1 (fr) *	2010-02-15	2012-12-07	St Microelectronics Sa	Cellule de memoire vive sram a dix transistors
KR101669244B1 (ko)	2010-06-08	2016-10-25	삼성전자주식회사	에스램 소자 및 그 제조방법
US9159627B2 (en)	2010-11-12	2015-10-13	Tela Innovations, Inc.	Methods for linewidth modification and apparatus implementing the same
US20120120703A1 (en) *	2010-11-15	2012-05-17	Taiwan Semiconductor Manufacturing Co., Ltd.	Memory device with asymmetrical bit cell arrays and balanced resistance and capacitance
US8717798B2 (en) *	2011-09-23	2014-05-06	Taiwan Semiconductor Manufacturing Co., Ltd.	Layout for semiconductor memories
JP6034764B2 (ja) *	2013-08-05	2016-11-30	ルネサスエレクトロニクス株式会社	半導体記憶装置
CN110010169B (zh) *	2018-01-04	2022-03-29	联华电子股份有限公司	双端口静态随机存取存储器单元

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JP3779734B2 (ja) *	1993-02-19	2006-05-31	株式会社ルネサステクノロジ	半導体集積回路装置およびその製造方法
US5754468A (en) *	1996-06-26	1998-05-19	Simon Fraser University	Compact multiport static random access memory cell
JP3523762B2 (ja) *	1996-12-19	2004-04-26	株式会社東芝	半導体記憶装置
JP3036588B2 (ja) *	1997-02-03	2000-04-24	日本電気株式会社	半導体記憶装置
JPH1145949A (ja) *	1997-07-28	1999-02-16	Mitsubishi Electric Corp	スタティック型半導体記憶装置およびその製造方法
US6026012A (en) *	1998-12-30	2000-02-15	United Microelectronic Corp.	Dual port random access memory
JP3526553B2 (ja) *	2001-01-26	2004-05-17	松下電器産業株式会社	Ｓｒａｍ装置
JP4623885B2 (ja) *	2001-08-16	2011-02-02	ルネサスエレクトロニクス株式会社	半導体記憶装置
US6670642B2 (en) *	2002-01-22	2003-12-30	Renesas Technology Corporation.	Semiconductor memory device using vertical-channel transistors
FR2843481B1 (fr) *	2002-08-08	2005-09-16	Soisic	Memoire sur substrat du type silicium sur isolant
KR100450683B1 (ko) *	2002-09-04	2004-10-01	삼성전자주식회사	Ｓｏｉ 기판에 형성되는 에스램 디바이스
JP4005468B2 (ja) *	2002-09-30	2007-11-07	富士通株式会社	メモリセルの配置方法及び半導体記憶装置
US6778462B1 (en) *	2003-05-08	2004-08-17	Lsi Logic Corporation	Metal-programmable single-port SRAM array for dual-port functionality
US7345909B2 (en) *	2003-09-24	2008-03-18	Yen-Jen Chang	Low-power SRAM memory cell
US7023056B2 (en) *	2003-11-26	2006-04-04	Taiwan Semiconductor Manufacturing Company, Ltd.	Memory cell structure
JP2005175415A (ja) *	2003-12-05	2005-06-30	Taiwan Semiconductor Manufacturing Co Ltd	集積回路デバイスとその製造方法

2005
- 2005-03-25 WO PCT/IB2005/001015 patent/WO2005096381A1/en active IP Right Grant
- 2005-03-25 DE DE602005002546T patent/DE602005002546T2/de not_active Expired - Lifetime
- 2005-03-25 JP JP2007505670A patent/JP5149617B2/ja not_active Expired - Fee Related
- 2005-03-25 EP EP05718464A patent/EP1730777B1/de not_active Expired - Lifetime
- 2005-03-25 US US11/547,549 patent/US7706172B2/en active Active
- 2005-03-25 AT AT05718464T patent/ATE373876T1/de not_active IP Right Cessation

Also Published As

Publication number	Publication date
JP5149617B2 (ja)	2013-02-20
US20080062756A1 (en)	2008-03-13
DE602005002546D1 (de)	2007-10-31
DE602005002546T2 (de)	2008-06-12
WO2005096381A1 (en)	2005-10-13
JP2007533122A (ja)	2007-11-15
EP1730777B1 (de)	2007-09-19
US7706172B2 (en)	2010-04-27
EP1730777A1 (de)	2006-12-13

Publication	Publication Date	Title
ATE373876T1 (de)	2007-10-15	Verbessertes layout einer sram-speicherzelle
US7016214B2 (en)	2006-03-21	Semiconductor integrated circuit device
WO2011133763A3 (en)	2012-02-09	Retain-till-accessed (rta) power saving mode in high performance static memories
TW200625331A (en)	2006-07-16	Memory cell array
US7616516B2 (en)	2009-11-10	Semiconductor device
JP2006085786A5 (de)	2007-10-18
US11798615B2 (en)	2023-10-24	High density array, in memory computing
ATE305173T1 (de)	2005-10-15	Statische speicherzelle
US11683924B2 (en)	2023-06-20	Memory device and manufacturing method
US10199380B2 (en)	2019-02-05	SRAM cell with T-shaped contact
US9336859B2 (en)	2016-05-10	Memory array
TW201525997A (zh)	2015-07-01	記憶體電路
JPWO2021125138A5 (de)	2022-08-15
US9177634B1 (en)	2015-11-03	Two gate pitch FPGA memory cell
US8929154B2 (en)	2015-01-06	Layout of memory cells
FR2853445B1 (fr)	2005-10-14	Cellule memoire statique a acces aleatoire(sram), et unite memoire a ultra basse consommation realisee a partir de telles cellules
CN114725109A (zh)	2022-07-08	静态随机存取存储器的布局图案及其形成方法
JP2005039294A (ja)	2005-02-10	半導体記憶装置
Sulaiman	2021	22 nm SRAM Design for Ultra-Low Power (ULP) Applications
US10163494B1 (en)	2018-12-25	Memory device and fabrication method thereof
KR100865633B1 (ko)	2008-10-27	듀얼 포트 에스램
KR930020431A (ko)	1993-10-19	특수한 배선 구성의 n-mos 메모리 셀을 갖는 반도체 메모리장치
KR940022555A (ko)	1994-10-21	저전력 소모형 비트선 구성회로
KR20110122411A (ko)	2011-11-10	Ｓｒａｍ 셀
JP2009048670A (ja)	2009-03-05	半導体回路

Legal Events

Date	Code	Title	Description
2008-03-15	RER	Ceased as to paragraph 5 lit. 3 law introducing patent treaties