ATE331245T1 - Leistungssteuerungsverfahren für ein rechnersystem mit einer knotenpunktarchitektur - Google Patents

Leistungssteuerungsverfahren für ein rechnersystem mit einer knotenpunktarchitektur

Info

Publication number: ATE331245T1
Authority: AT; Austria
Prior art keywords: computer system; control method; power control; node architecture; hub
Prior art date: 1999-10-07

Application number

AT00982616T

Other languages

English (en)

Inventor

David J Harriman

David I Poisner

Jeff Rabe

Original Assignee

Intel Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1999-10-07

Filing date

2000-09-26

Publication date

2006-07-15

2000-09-26 Application filed by Intel Corp filed Critical Intel Corp

2006-07-15 Application granted granted Critical

2006-07-15 Publication of ATE331245T1 publication Critical patent/ATE331245T1/de

Classifications

- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3253—Power saving in bus
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

Engineering & Computer Science (AREA)
Theoretical Computer Science (AREA)
Physics & Mathematics (AREA)
General Engineering & Computer Science (AREA)
General Physics & Mathematics (AREA)
Multi Processors (AREA)
Stored Programmes (AREA)
Power Sources (AREA)
Information Transfer Systems (AREA)
Data Exchanges In Wide-Area Networks (AREA)

AT00982616T 1999-10-07 2000-09-26 Leistungssteuerungsverfahren für ein rechnersystem mit einer knotenpunktarchitektur ATE331245T1 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
US09/414,999 US6480965B1 (en)	1999-10-07	1999-10-07	Power management method for a computer system having a hub interface architecture

Publications (1)

Publication Number	Publication Date
ATE331245T1 true ATE331245T1 (de)	2006-07-15

Family

ID=23643929

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
AT00982616T ATE331245T1 (de)	1999-10-07	2000-09-26	Leistungssteuerungsverfahren für ein rechnersystem mit einer knotenpunktarchitektur

Country Status (8)

Country	Link
US (1)	US6480965B1 (de)
EP (1)	EP1222516B1 (de)
AT (1)	ATE331245T1 (de)
AU (1)	AU1962401A (de)
DE (1)	DE60028992T2 (de)
HK (1)	HK1045201B (de)
TW (1)	TW476026B (de)
WO (1)	WO2001025886A2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US7039047B1 (en)	1999-11-03	2006-05-02	Intel Corporation	Virtual wire signaling
US6633987B2 (en) *	2000-03-24	2003-10-14	Intel Corporation	Method and apparatus to implement the ACPI(advanced configuration and power interface) C3 state in a RDRAM based system
US7099318B2 (en) *	2001-12-28	2006-08-29	Intel Corporation	Communicating message request transaction types between agents in a computer system using multiple message groups
US7114038B2 (en) *	2001-12-28	2006-09-26	Intel Corporation	Method and apparatus for communicating between integrated circuits in a low power mode
US7469350B2 (en) *	2005-12-22	2008-12-23	Ncr Corporation	Power control interface for a self-service apparatus
US8566628B2 (en) *	2009-05-06	2013-10-22	Advanced Micro Devices, Inc.	North-bridge to south-bridge protocol for placing processor in low power state
US20110112798A1 (en) *	2009-11-06	2011-05-12	Alexander Branover	Controlling performance/power by frequency control of the responding node
EP2391056B1 (de) *	2010-05-26	2013-08-21	Samsung Electronics Co., Ltd.	Medienspieler und Verfahren zur Rückholung aus dem Ruhemodus
US8438416B2 (en) *	2010-10-21	2013-05-07	Advanced Micro Devices, Inc.	Function based dynamic power control
RU2617549C2 (ru) *	2011-07-06	2017-04-25	Телефонактиеболагет Л М Эрикссон(Пабл)	Способ управления обменами транзакциями между двумя интегральными схемами

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US5687388A (en)	1992-12-08	1997-11-11	Compaq Computer Corporation	Scalable tree structured high speed input/output subsystem architecture
US5675813A (en)	1995-10-26	1997-10-07	Microsoft Corporation	System and method for power control in a universal serial bus
US5799196A (en)	1996-07-02	1998-08-25	Gateway 2000, Inc.	Method and apparatus of providing power management using a self-powered universal serial bus (USB) device
KR100218003B1 (ko) *	1997-04-22	1999-09-01	윤종용	Usb 허브 전원을 이용한 디스플레이 장치의 전원 제어장치 및 제어방법
US6151262A (en) *	1998-10-28	2000-11-21	Texas Instruments Incorporated	Apparatus, system and method for control of speed of operation and power consumption of a memory
US6141283A (en) *	1999-04-01	2000-10-31	Intel Corporation	Method and apparatus for dynamically placing portions of a memory in a reduced power consumption state

1999
- 1999-10-07 US US09/414,999 patent/US6480965B1/en not_active Expired - Lifetime
2000
- 2000-09-26 DE DE60028992T patent/DE60028992T2/de not_active Expired - Lifetime
- 2000-09-26 WO PCT/US2000/040998 patent/WO2001025886A2/en active IP Right Grant
- 2000-09-26 AU AU19624/01A patent/AU1962401A/en not_active Abandoned
- 2000-09-26 EP EP00982616A patent/EP1222516B1/de not_active Expired - Lifetime
- 2000-09-26 AT AT00982616T patent/ATE331245T1/de not_active IP Right Cessation
- 2000-10-24 TW TW089121005A patent/TW476026B/zh not_active IP Right Cessation
2002
- 2002-09-05 HK HK02106552.5A patent/HK1045201B/zh not_active IP Right Cessation

Also Published As

Publication number	Publication date
WO2001025886A3 (en)	2002-02-14
DE60028992D1 (de)	2006-08-03
EP1222516A2 (de)	2002-07-17
DE60028992T2 (de)	2007-02-01
EP1222516B1 (de)	2006-06-21
AU1962401A (en)	2001-05-10
HK1045201B (zh)	2006-11-10
WO2001025886A9 (en)	2002-08-01
US6480965B1 (en)	2002-11-12
TW476026B (en)	2002-02-11
HK1045201A1 (en)	2002-11-15
WO2001025886A2 (en)	2001-04-12

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Legal Events

Date	Code	Title	Description
2006-12-15	RER	Ceased as to paragraph 5 lit. 3 law introducing patent treaties