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ATE120909T1 - Anordnung zum einfügen binärer informationselemente in eine bestimmte rahmenstruktur. - Google Patents

Anordnung zum einfügen binärer informationselemente in eine bestimmte rahmenstruktur.

Info

Publication number
ATE120909T1
ATE120909T1 AT90124539T AT90124539T ATE120909T1 AT E120909 T1 ATE120909 T1 AT E120909T1 AT 90124539 T AT90124539 T AT 90124539T AT 90124539 T AT90124539 T AT 90124539T AT E120909 T1 ATE120909 T1 AT E120909T1
Authority
AT
Austria
Prior art keywords
memory
binary elements
arrangement
frame structure
information elements
Prior art date
Application number
AT90124539T
Other languages
English (en)
Inventor
Philippe Regent
Original Assignee
Cit Alcatel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cit Alcatel filed Critical Cit Alcatel
Application granted granted Critical
Publication of ATE120909T1 publication Critical patent/ATE120909T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/12—Arrangements providing for calling or supervisory signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Communication Control (AREA)
  • Mirrors, Picture Frames, Photograph Stands, And Related Fastening Devices (AREA)
  • Holo Graphy (AREA)
  • Television Systems (AREA)
AT90124539T 1989-12-27 1990-12-18 Anordnung zum einfügen binärer informationselemente in eine bestimmte rahmenstruktur. ATE120909T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8917256A FR2656479B1 (de) 1989-12-27 1989-12-27

Publications (1)

Publication Number Publication Date
ATE120909T1 true ATE120909T1 (de) 1995-04-15

Family

ID=9389013

Family Applications (1)

Application Number Title Priority Date Filing Date
AT90124539T ATE120909T1 (de) 1989-12-27 1990-12-18 Anordnung zum einfügen binärer informationselemente in eine bestimmte rahmenstruktur.

Country Status (8)

Country Link
EP (1) EP0435130B1 (de)
JP (1) JPH0761056B2 (de)
AT (1) ATE120909T1 (de)
AU (1) AU640727B2 (de)
CA (1) CA2033156C (de)
DE (1) DE69018411T2 (de)
ES (1) ES2071736T3 (de)
FR (1) FR2656479B1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04137993A (ja) * 1990-09-28 1992-05-12 Fujitsu Ltd サブレート時間スイッチ
FR2680062A1 (fr) * 1991-07-31 1993-02-05 Cit Alcatel Dispositif d'extraction d'elements binaires d'information d'une structure de trame determinee.
ES2046106B1 (es) * 1992-02-18 1996-11-16 Estandard Electrica S A Metodo de realizacion de circuitos alineadores inmunes a los deslizamientos ocurridos en la memoria elastica de recepcion.
FI90486C (fi) * 1992-06-03 1999-08-11 Nokia Telecommunications Oy Menetelmä ja laite synkronisessa digitaalisessa tietoliikennejärjestelmässä suoritettavan elastisen puskuroinnin toteuttamiseksi
FI90485C (fi) * 1992-06-03 1999-08-11 Nokia Telecommunications Oy Menetelmä osoittimia sisältävien kehysrakenteiden purkamiseksi ja muodostamiseksi
FI90484C (fi) * 1992-06-03 1999-08-11 Nokia Telecommunications Oy Menetelmä ja laite synkronisessa digitaalisessa tietoliikennejärjestelmässä käytettävän elastisen puskurimuistin täyttöasteen valvomiseksi
US5327126A (en) * 1992-06-26 1994-07-05 Hewlett-Packard Company Apparatus for and method of parallel justifying and dejustifying data in accordance with a predetermined mapping
AU664097B2 (en) * 1992-06-26 1995-11-02 Hewlett-Packard Australia Limited A justifier and de-justifier

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2641488C2 (de) * 1976-09-15 1978-11-16 Siemens Ag, 1000 Berlin Und 8000 Muenchen Schaltungsanordnung zum Phasenausgleich bei PCM-Vermittlungsstellen
DE3600795A1 (de) * 1986-01-14 1987-07-16 Ant Nachrichtentech Digitales nachrichtenuebertragungssystem
JPH01123542A (ja) * 1987-11-09 1989-05-16 Nec Corp 端局中継装置
JPH0644746B2 (ja) * 1988-03-25 1994-06-08 富士通株式会社 並列型パルス挿入回路

Also Published As

Publication number Publication date
AU6843490A (en) 1991-07-04
JPH04211535A (ja) 1992-08-03
DE69018411T2 (de) 1995-08-03
AU640727B2 (en) 1993-09-02
CA2033156A1 (fr) 1991-06-28
ES2071736T3 (es) 1995-07-01
DE69018411D1 (de) 1995-05-11
JPH0761056B2 (ja) 1995-06-28
CA2033156C (fr) 1994-08-16
EP0435130B1 (de) 1995-04-05
FR2656479A1 (de) 1991-06-28
FR2656479B1 (de) 1994-04-08
EP0435130A1 (de) 1991-07-03

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Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee