... 4). Tak-ing the oneslot system into account, a controller module must be reconfigured and executed within one sample pe-riod. Here, tonesiot (eq. ... Computing the outer sum sequentially is called 1-BAAT (one bit at a time) and takes... more
... 4). Tak-ing the oneslot system into account, a controller module must be reconfigured and executed within one sample pe-riod. Here, tonesiot (eq. ... Computing the outer sum sequentially is called 1-BAAT (one bit at a time) and takes w clock cycles. ...
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Control systems can be implemented in reconfigurable hardware as an efficient and high-performance alternative to control algorithms executed by processors [4, 7, 10]. The large design space offered by reconfigurable hardware allows an... more
Control systems can be implemented in reconfigurable hardware as an efficient and high-performance alternative to control algorithms executed by processors [4, 7, 10]. The large design space offered by reconfigurable hardware allows an exploration of different area/time trade-offs and to ...
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ABSTRACT
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... Modern CMPs Gilles Pokam Intel Corporation gilles.a.pokam@intel.com Cristiano Pereira Intel Corporation cristiano.l.pereira@intel.com Klaus Danne Intel Corporation klaus.danne@intel.com Rolf Kassa Intel Corporation... more
... Modern CMPs Gilles Pokam Intel Corporation gilles.a.pokam@intel.com Cristiano Pereira Intel Corporation cristiano.l.pereira@intel.com Klaus Danne Intel Corporation klaus.danne@intel.com Rolf Kassa Intel Corporation rolf.kassa@intel.com ...
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This paper presents the architecture of an operating system (called NanoOS) for applications distributed over mobile ad hoc networks (MANETs). Furthermore, a service distribution method inspired on the foraging behavior of ants is... more
This paper presents the architecture of an operating system (called NanoOS) for applications distributed over mobile ad hoc networks (MANETs). Furthermore, a service distribution method inspired on the foraging behavior of ants is proposed. The NanoOS offers an uniform ...
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ABSTRACT
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The partial runtime reconfiguration capability of FPGAs allows task execution in a multitasking manner. In contrasts to most other models, we assume that each task has several implementation variants with different performance and size.... more
The partial runtime reconfiguration capability of FPGAs allows task execution in a multitasking manner. In contrasts to most other models, we assume that each task has several implementation variants with different performance and size. Moreover, one task variant is an extension of another. Therefore, a task can change between its variants without reconfiguring the entire task footprint. As case study, we introduce an online scalable distributed arithmetic design and review the advantages.
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In this paper, we consider the scheduling of periodic real-time tasks on reconfigurable hardware devices. Such devices can execute several tasks in parallel. All executing tasks share the hardware resource, which makes the scheduling... more
In this paper, we consider the scheduling of periodic real-time tasks on reconfigurable hardware devices. Such devices can execute several tasks in parallel. All executing tasks share the hardware resource, which makes the scheduling problem differ from single- and multiprocessor scheduling. We adapt the global EDF multiprocessor scheduling approach to the reconfigurable hardware execution model and define two preemptive scheduling algorithms, EDF-First-k-Fit and EDF-Next-Fit . For these algorithms, we present a novel linear-time schedulability test and give a proof based on a resource augmentation technique. Then, we propose a task placement and relocation scheme utilizing partial device reconfiguration. This scheme allows us to extend the schedulability test to include reconfiguration time overheads. Experiments with synthetic workloads compare the scheduling test with the actual scheduling performance of EDF-First-k-Fit and EDF-Next-Fit . The main evaluation result is that the re...
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This paper deals with scheduling periodic real-time tasks on reconfigurable hardware devices, such as FPGAs. Re- configurable hardware devices are increasingly used in em- bedded systems. To utilize these devices also for systems with... more
This paper deals with scheduling periodic real-time tasks on reconfigurable hardware devices, such as FPGAs. Re- configurable hardware devices are increasingly used in em- bedded systems. To utilize these devices also for systems with real-time constraints, predictable task scheduling is re- quired. We formalize the periodic task scheduling problem and propose two preemptive scheduling algorithms. The first is an adaption
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ABSTRACT
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... B) Each task implements a function to save/load its context (state registers) to/from an interface connected to external memory. Therefore, the task can store its context beforeit is interrupted and can read it back when it resumes... more
... B) Each task implements a function to save/load its context (state registers) to/from an interface connected to external memory. Therefore, the task can store its context beforeit is interrupted and can read it back when it resumes its execution. ...
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Use cases: Deterministically reconstructing a program execution has several use cases. First, it can be used to debug programs by being able to reconstruct a bug and observing the situation in enhanced debugging tools. Such tools can for... more
Use cases: Deterministically reconstructing a program execution has several use cases. First, it can be used to debug programs by being able to reconstruct a bug and observing the situation in enhanced debugging tools. Such tools can for example allow the illusion of ...
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Abstract: We present a tool for design and implementation of reconfigurable compu-ting applications based on the use of distributed arithmetic. Our tool provides the user the possibility to investigate different tradeoffs like area vs... more
Abstract: We present a tool for design and implementation of reconfigurable compu-ting applications based on the use of distributed arithmetic. Our tool provides the user the possibility to investigate different tradeoffs like area vs speed for his design. After simulation of the design, a ...
Research Interests: Computer Science and Arcs
This paper presents work in progress on executing real- time applications on FPGA-based computing systems. Usu- ally, these systems provide an FPGA device coupled with multiple external SRAM banks. Todays FPGAs show large capacities and... more
This paper presents work in progress on executing real- time applications on FPGA-based computing systems. Usu- ally, these systems provide an FPGA device coupled with multiple external SRAM banks. Todays FPGAs show large capacities and are reprogrammable during runtime, al- lowing for space- and time-sharing multitasking. Typical FPGA tasks demand large memory buffers and access them periodically. In our previous work, we have devised tech- niques for scheduling periodic real-time tasks to such sys- tems. In this paper, we address the resulting problem of as- signing data buffers to physical memories, and aim at min- imizing the number of required memories for a given appli- cation. We model the minimization problem as an integer linear program and present first results.