Research Interests: Routing, Routing algorithm, Computer Hardware, Soc, Vhdl, and 18 morePerformance Evaluation, Adaptive, Power Consumption, Performance Improvement, Low Power Consumption, Microprocessors, NoC, High performance, Adaptive Routing, High Speed, Real Time Application, Network on chip, MESH NETWORK, Deterministic, Torus, Electrical And Electronic Engineering, Virtual Channel, and power efficiency
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ABSTRACT
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ABSTRACT This tutorial reviews four popular mathematical formalisms -- dataflow analysis, schedulability analysis, network calculus, and queueing theory -- and how they have been applied to the analysis of Network-on-Chip (NoC)... more
ABSTRACT This tutorial reviews four popular mathematical formalisms -- dataflow analysis, schedulability analysis, network calculus, and queueing theory -- and how they have been applied to the analysis of Network-on-Chip (NoC) performance. We review the basic concepts and results of each formalism and provide examples of how they have been used in on-chip communication performance analysis. The tutorial also discusses the respective strengths and weaknesses of each formalism, their suitability for a specific purpose, and the attempts that have been made to bridge these analytical approaches. Finally, we conclude the tutorial by discussing open research issues.
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Future system-on-chip (SoC) designs will need efficient on-chip communication architectures that can provide efficient and scalable data transport among the intellectual properties (IPs). Designing and optimizing SoCs is an increasingly... more
Future system-on-chip (SoC) designs will need efficient on-chip communication architectures that can provide efficient and scalable data transport among the intellectual properties (IPs). Designing and optimizing SoCs is an increasingly difficult task due to the size and complexity of the SoC design space, high cost of detailed simulation, and several constraints that the design must satisfy. For efficient design of
Research Interests: Intellectual Property, Routing, Intellectual Properties, System on Chip, Chip, and 13 moreDesign optimization, Network Routing, Analytical Model, System on a Chip, Network on chip, Network Topology, Logic Design, Boolean Satisfiability, DESIGN SPACE, Cost Function, Network on a Chip, Communication Delay, and Wormhole routing
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7he star graph was introduced as an attractive alternative to the well-know hypercube and its prop-erties have been well studied in the past. Most of these studies have focused on topo/ogical properties and algorithmic aspects of this... more
7he star graph was introduced as an attractive alternative to the well-know hypercube and its prop-erties have been well studied in the past. Most of these studies have focused on topo/ogical properties and algorithmic aspects of this network Im this paper, the performance of nine ...
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ABSTRACT We propose an analytical model based on queueing theory for delay analysis in a wormhole-switched network-on-chip (NoC). The proposed model takes as input an application communication graph, a topology graph, a mapping vector,... more
ABSTRACT We propose an analytical model based on queueing theory for delay analysis in a wormhole-switched network-on-chip (NoC). The proposed model takes as input an application communication graph, a topology graph, a mapping vector, and a routing matrix, and estimates average packet latency and router blocking time. It works for arbitrary network topology with deterministic routing under arbitrary traffic patterns. This model can estimate per-flow average latency accurately and quickly, thus enabling fast design space exploration of various design parameters in NoC designs. Experimental results show that the proposed analytical model can predict the average packet latency more than four orders of magnitude faster than an accurate simulation, while the computation error is less than 10% in non-saturated networks for different system-on-chip platforms.
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ABSTRACT This article reviews four popular mathematical formalisms—queueing theory, network calculus, schedulability analysis, and dataflow analysis—and how they have been applied to the analysis of on-chip communication performance in... more
ABSTRACT This article reviews four popular mathematical formalisms—queueing theory, network calculus, schedulability analysis, and dataflow analysis—and how they have been applied to the analysis of on-chip communication performance in Systems-on-Chip. The article discusses the basic concepts and results of each formalism and provides examples of how they have been used in Networks-on-Chip (NoCs) performance analysis. Also, the respective strengths and weaknesses of each technique and its suitability for a specific purpose are investigated. An open research issue is a unified analytical model for a comprehensive performance evaluation of NoCs. To this end, this article reviews the attempts that have been made to bridge these formalisms.