Add --trace-saif for SAIF power traces
#5812
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Note please merge in master to make sure you have the latest github actions correct. |
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
…g instead of assert
I've looked into that PR and reorganized activity accumulation code as @gezalore suggested in #5812 (comment). To implement a similar multithreaded trace it should be a matter of creating more instances of verilator/include/verilated_fst_c.cpp Line 148 in 2929e50 VerilatedSaifBuffer trace buffer object when emitting variable changes. As I understood correctly, fidx argument in declare* functions is index value of which target file/accumulation object should receive this variable.
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I think that's a reasonable way to extend it. Let me know when you think all your updates are otherwise done and I'll re-review. |
All changes suggested by review comments are done. It is ready for re-review. |
True, but you can also map multiple fidx into the same file if you want. All the tracing callbacks that are registered with a given fidx, will be called with a trace buffer created with the same fidx, and trace the variables declared with the same fidx, that's all there is to it. |
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The github actions were not run, can you getthem working? We get email on every push and it's been a lot of mail. ;) please debug and get it ready on a separate personal branch, and push to this branch only when tests passing and you think it is ready for final review, thanks. |
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Sorry about the spam. Edit: This commit seems to introduce the bug. Opened a new issue for it: #5834 |
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Sorry for the problem. Code is ready for final review as the bug causing CI to fail was fixed and all checks finished successfully. |
This PR adds the possibility of dumping SAIF files (see Annex I) with
--trace-saifflag, which can further be used as an input for design static power analysis in tools like OpenSTA. Example workflow of this process can be found here.SAIF has an advantage over VCD format in terms of file size - SAIF trace saves accumulated statistics accumulated of signals in the form of their toggle count and time when bit was low/high instead of every change that happened during the simulation trace.
While VCD files can easily grow to gigabytes in size, SAIF usually takes up kilobytes and does not grow with simulation time. This speeds up processing by power analysis tools.