8000 [#74021] add t_trace_saif_sc test · verilator/verilator@3c148bc · GitHub
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magancarzmagancarz
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[#74021] add t_trace_saif_sc test
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‎test_regress/t/t_trace_saif_sc.out

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(SAIFILE
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(SAIFVERSION "2.0")
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(DIRECTION "backward")
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(DESIGN "t")
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(DIVIDER / )
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(TIMESCALE 1ps)
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(DURATION 1004)
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(INSTANCE top
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(INSTANCE t
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(NET
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(clk (T0 505) (T1 499) (TX 0) (TC 199))
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(cyc\[0\] (T0 504) (T1 500) (TX 0) (TC 100))
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(cyc\[1\] (T0 504) (T1 500) (TX 0) (TC 50))
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(cyc\[2\] (T0 520) (T1 484) (TX 0) (TC 25))
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(cyc\[3\] (T0 524) (T1 480) (TX 0) (TC 12))
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(cyc\[4\] (T0 524) (T 10000 1 480) (TX 0) (TC 6))
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(cyc\[5\] (T0 640) (T1 364) (TX 0) (TC 3))
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(cyc\[6\] (T0 640) (T1 364) (TX 0) (TC 1))
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(rstn (T0 110) (T1 894) (TX 0) (TC 1))
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(fst_parameter\[0\] (T0 0) (T1 1004) (TX 0) (TC 1))
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(fst_parameter\[1\] (T0 0) (T1 1004) (TX 0) (TC 1))
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(fst_parameter\[3\] (T0 0) (T1 1004) (TX 0) (TC 1))
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(fst_parameter\[4\] (T0 0) (T1 1004) (TX 0) (TC 1))
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(fst_parameter\[5\] (T0 0) (T1 1004) (TX 0) (TC 1))
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(fst_parameter\[6\] (T0 0) (T1 1004) (TX 0) (TC 1))
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(fst_lparam\[3\] (T0 0) (T1 1004) (TX 0) (TC 1))
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(fst_lparam\[6\] (T0 0) (T1 1004) (TX 0) (TC 1))
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(fst_lparam\[7\] (T0 0) (T1 1004) (TX 0) (TC 1))
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(fst_lparam\[8\] (T0 0) (T1 1004) (TX 0) (TC 1))
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(fst_supply1 (T0 0) (T1 1004) (TX 0) (TC 1))
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(fst_tri1 (T0 0) (T1 1004) (TX 0) (TC 1))
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(state\[0\] (T0 414) (T1 590) (TX 0) (TC 46))
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(state\[1\] (T0 540) (T1 464) (TX 0) (TC 45))
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(state\[2\] (T0 534) (T1 470) (TX 0) (TC 46))
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(state\[3\] (T0 544) (T1 460) (TX 0) (TC 44))
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(state\[4\] (T0 540) (T1 464) (TX 0) (TC 45))
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)
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(INSTANCE test
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(NET
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(clk (T0 505) (T1 499) (TX 0) (TC 199))
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(rstn (T0 110) (T1 894) (TX 0) (TC 1))
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(state\[0\] (T0 414) (T1 590) (TX 0) (TC 46))
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(state\[1\] (T0 540) (T1 464) (TX 0) (TC 45))
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(state\[2\] (T0 534) (T1 470) (TX 0) (TC 46))
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(state\[3\] (T0 544) (T1 460) (TX 0) (TC 44))
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(state\[4\] (T0 540) (T1 464) (TX 0) (TC 45))
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(state_w\[0\] (T0 534) (T1 470) (TX 0) (TC 46))
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(state_w\[1\] (T0 534) (T1 470) (TX 0) (TC 46))
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(state_w\[2\] (T0 434) (T1 570) (TX 0) (TC 46))
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(state_w\[3\] (T0 530) (T1 474) (TX 0) (TC 47))
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(state_w\[4\] (T0 424) (T1 580) (TX 0) (TC 48))
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(state_array[0]\[0\] (T0 414) (T1 590) (TX 0) (TC 46))
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(state_array[0]\[1\] (T0 540) (T1 464) (TX 0) (TC 45))
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(state_array[0]\[2\] (T0 534) (T1 470) (TX 0) (TC 46))
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(state_array[0]\[3\] (T0 544) (T1 460) (TX 0) (TC 44))
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(state_array[0]\[4\] (T0 540) (T1 464) (TX 0) (TC 45))
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(state_array[1]\[0\] (T0 420) (T1 584) (TX 0) (TC 47))
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(state_array[1]\[1\] (T0 534) (T1 470) (TX 0) (TC 46))
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(state_array[1]\[2\] (T0 534) (T1 470) (TX 0) (TC 46))
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(state_array[1]\[3\] (T0 540) (T1 464) (TX 0) (TC 45))
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(state_array[1]\[4\] (T0 534) (T1 470) (TX 0) (TC 46))
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(state_array[2]\[0\] (T0 424) (T1 580) (TX 0) (TC 48))
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(state_array[2]\[1\] (T0 534) (T1 470) (TX 0) (TC 46))
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(state_array[2]\[2\] (T0 534) (T1 470) (TX 0) (TC 46))
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(state_array[2]\[3\] (T0 534) (T1 470) (TX 0) (TC 46))
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(state_array[2]\[4\] (T0 530) (T1 474) (TX 0) (TC 47))
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)
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(INSTANCE unnamedblk1
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(NET
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(i\[0\] (T0 10) (T1 994) (TX 0) (TC 1))
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(i\[1\] (T0 10) (T1 994) (TX 0) (TC 1))
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)
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)
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(INSTANCE unnamedblk2
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(NET
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(i\[1\] (T0 120) (T1 884) (TX 0) (TC 1))
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)
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)
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)
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)
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)
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)

‎test_regress/t/t_trace_saif_sc.py

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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt_all')
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if not test.have_sc:
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test.skip("No SystemC installed")
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test.compile(verilator_flags2=["--trace-saif --sc"])
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test.execute()
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test.fst_identical(test.trace_filename, test.golden_filename)
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test.passes()

‎test_regress/t/t_trace_saif_sc.v

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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int cyc;
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reg rstn;
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parameter real fst_gparam_real = 1.23;
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localparam real fst_lparam_real = 4.56;
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real fst_real = 1.23;
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integer fst_integer;
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bit fst_bit;
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logic fst_logic;
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int fst_int;
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shortint fst_shortint;
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longint fst_longint;
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byte fst_byte;
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parameter fst_parameter = 123;
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localparam fst_lparam = 456;
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supply0 fst_supply0;
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supply1 fst_supply1;
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tri0 fst_tri0;
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tri1 fst_tri1;
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tri fst_tri;
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wire fst_wire;
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logic [4:0] state;
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Test test (/*AUTOINST*/
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// Outputs
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.state (state[4:0]),
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// Inputs
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.clk (clk),
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.rstn (rstn));
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// Test loop
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc==0) begin
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// Setup
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rstn <= ~'1;
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end
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else if (cyc<10) begin
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rstn <= ~'1;
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end
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else if (cyc<90) begin
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rstn <= ~'0;
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end
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else if (cyc==99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test (
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input clk,
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input rstn,
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output logic [4:0] state
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);
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logic [4:0] state_w;
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logic [4:0] state_array [3];
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assign state = state_array[0];
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always_comb begin
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state_w[4] = state_array[2][0];
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state_w[3] = state_array[2][4];
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state_w[2] = state_array[2][3] ^ state_array[2][0];
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state_w[1] = state_array[2][2];
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state_w[0] = state_array[2][1];
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end
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always_ff @(posedge clk or negedge rstn) begin
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if (!rstn) begin
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for (int i = 0; i < 3; i++)
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state_array[i] <= 'b1;
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end
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else begin
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for (int i = 0; i < 2; i++)
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state_array[i] <= state_array[i+1];
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state_array[2] <= state_w;
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end
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end
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endmodule

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