🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
-
Updated
Aug 25, 2024 - VHDL
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
Image Processing Toolbox in Verilog using Basys3 FPGA
Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
VHDL Guide
Trying to verify Verilog/VHDL designs with formal methods and tools
cryptography ip-cores in vhdl / verilog
The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).
Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions. Nios just reads the FFT result and draws the display bars. VGA frame buffer on-chip. VGA signals generated on-chip. See the included video files to watch it in action.
Colorspace conversion, gamma correction, and more -- all integrated within a MIPI-to-HDMI pipeline in FPGA.
Verilog Convolutional Neural Network on PYNQ
Commodore 64 core for the MEGA65 based on the MiSTer FPGA C64 core
Add a description, image, and links to the verilog topic page so that developers can more easily learn about it.
To associate your repository with the verilog topic, visit your repo's landing page and select "manage topics."