8000 systemverilog-parser · GitHub Topics · GitHub

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systemverilog-parser

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verible

chipsalliance / verible

Star < 8000 span id="repo-stars-counter-star" aria-label="1466 users starred this repository" data-singular-suffix="user starred this repository" data-plural-suffix="users starred this repository" data-turbo-replace="true" title="1,466" data-view-component="true" class="Counter js-social-count">1.5k

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

productivity parser formatter analysis style-linter linter language-server-protocol syntax-tree lexer yacc systemverilog hacktoberfest lsp-server systemverilog-parser systemverilog-developer sv-lrm verible

Updated Feb 17, 2025
C++

Nic30 / hdlConvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

python parser fpga vhdl verilog systemverilog vhdl-parser antrl4 systemverilog-parser verilog-parser

Updated Sep 3, 2024
C++

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