RTL description, synthesis and physical design of a 4-stage pipelined 32bit RISC processor
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Updated
Dec 22, 2022 - Verilog
RTL description, synthesis and physical design of a 4-stage pipelined 32bit RISC processor
DLX microprocessor described in VHDL for the Microelectronic Systems course @ Politecnico di Torino
An assembler that converts dlx-format instructions to 32-bit binaries
Computer Architectures - Practical Assignment #2:
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