8000 Another upstream merge + build system fix by alexcrichton · Pull Request #9 · rust-lang/llvm-project · GitHub
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Merged
merged 10 commits into from
Feb 26, 2019
Merged

Another upstream merge + build system fix #9

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16667e0
ReleaseNotes: drop mention of -ftrivial-auto-var-init=zero
zmodem Feb 25, 2019
bb92074
Release notes for OpenCL
Feb 25, 2019
0777c34
ReleaseNotes: ARM64 SEH, pointed out by David Major
zmodem Feb 26, 2019
ee57e9e
Merging r354764:
zmodem Feb 26, 2019
e745d6d
Merging r354756:
zmodem Feb 26, 2019
319e7df
Merging r354721:
zmodem Feb 26, 2019
35782c5
Merging r354723:
zmodem Feb 26, 2019
e56517b
Merging r354733:
zmodem Feb 26, 2019
d77d0f8
Merge remote-tracking branch 'llvm/release/8.x' into rustc/8.0-2019-0…
alexcrichton Feb 26, 2019
f6605a6
Delete version check for clang-cl
alexcrichton Feb 26, 2019
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Merging r354733: 
------------------------------------------------------------------------
r354733 | nikic | 2019-02-23 19:59:01 +0100 (Sat, 23 Feb 2019) | 10 lines

[WebAssembly] Fix select of and (PR40805)

Fixes https://bugs.llvm.org/show_bug.cgi?id=40805 introduced by
patterns added in D53676.

I'm removing the patterns entirely here, as they are not correct
in the general case. If necessary something more specific can be
added in the future.

Differential Revision: https://reviews.llvm.org/D58575
------------------------------------------------------------------------

llvm-svn: 354860
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@zmodem
zmodem committed Feb 26, 2019
commit e56517b25e9ef43fbc5bb3473235b7fe00bb9497
7 changes: 0 additions & 7 deletions llvm/lib/Target/WebAssembly/WebAssemblyInstrInteger.td
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Original file line number Diff line number Diff line change
Expand Up @@ -122,10 +122,3 @@ def : Pat<(select (i32 (seteq I32:$cond, 0)), I32:$lhs, I32:$rhs),
(SELECT_I32 I32:$rhs, I32:$lhs, I32:$cond)>;
def : Pat<(select (i32 (seteq I32:$cond, 0)), I64:$lhs, I64:$rhs),
(SELECT_I64 I64:$rhs, I64:$lhs, I32:$cond)>;

// The legalizer inserts an unnecessary `and 1` to make input conform
// to getBooleanContents, which we can lower away.
def : Pat<(select (i32 (and I32:$cond, 1)), I32:$lhs, I32:$rhs),
(SELECT_I32 I32:$lhs, I32:$rhs, I32:$cond)>;
def : Pat<(select (i32 (and I32:$cond, 1)), I64:$lhs, I64:$rhs),
(SELECT_I64 I64:$lhs, I64:$rhs, I32:$cond)>;
25 changes: 21 additions & 4 deletions llvm/test/CodeGen/WebAssembly/select.ll
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Expand Up @@ -17,8 +17,10 @@ define i32 @select_i32_bool(i1 zeroext %a, i32 %b, i32 %c) {

; CHECK-LABEL: select_i32_bool_nozext:
; CHECK-NEXT: .functype select_i32_bool_nozext (i32, i32, i32) -> (i32){{$}}
; SLOW-NEXT: i32.select $push0=, $1, $2, $0{{$}}
; SLOW-NEXT: return $pop0{{$}}
; SLOW-NEXT: i32.const $push0=, 1{{$}}
; SLOW-NEXT: i32.and $push1=, $0, $pop0{{$}}
; SLOW-NEXT: i32.select $push2=, $1, $2, $pop1{{$}}
; SLOW-NEXT: return $pop2{{$}}
define i32 @select_i32_bool_nozext(i1 %a, i32 %b, i32 %c) {
%cond = select i1 %a, i32 %b, i32 %c
ret i32 %cond
Expand Down Expand Up @@ -55,8 +57,10 @@ define i64 @select_i64_bool(i1 zeroext %a, i64 %b, i64 %c) {

; CHECK-LABEL: select_i64_bool_nozext:
; CHECK-NEXT: .functype select_i64_bool_nozext (i32, i64, i64) -> (i64){{$}}
; SLOW-NEXT: i64.select $push0=, $1, $2, $0{{$}}
; SLOW-NEXT: return $pop0{{$}}
; SLOW-NEXT: i32.const $push0=, 1{{$}}
; SLOW-NEXT: i32.and $push1=, $0, $pop0{{$}}
; SLOW-NEXT: i64.select $push2=, $1, $2, $pop1{{$}}
; SLOW-NEXT: return $pop2{{$}}
define i64 @select_i64_bool_nozext(i1 %a, i64 %b, i64 %c) {
%cond = select i1 %a, i64 %b, i64 %c
ret i64 %cond
Expand Down Expand Up @@ -157,3 +161,16 @@ define double @select_f64_ne(i32 %a, double %b, double %c) {
%cond = select i1 %cmp, double %b, double %c
ret double %cond
}

; CHECK-LABEL: pr40805:
; CHECK-NEXT: .functype pr40805 (i32, i32, i32) -> (i32){{$}}
; SLOW-NEXT: i32.const $push0=, 1{{$}}
; SLOW-NEXT: i32.and $push1=, $0, $pop0{{$}}
; SLOW-NEXT: i32.select $push2=, $1, $2, $pop1{{$}}
; SLOW-NEXT: return $pop2{{$}}
define i32 @pr40805(i32 %x, i32 %y, i32 %z) {
%a = and i32 %x, 1
%b = icmp ne i32 %a, 0
%c = select i1 %b, i32 %y, i32 %z
ret i32 %c
}
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/WebAssembly/simd-select.ll
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Expand Up @@ -29,7 +29,7 @@ define <16 x i8> @vselect_v16i8(<16 x i1> %c, <16 x i8> %x, <16 x i8> %y) {
; CHECK-NEXT: i8x16.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <16 x i8> @select_v16i8(i1 %c, <16 x i8> %x, <16 x i8> %y) {
define <16 x i8> @select_v16i8(i1 zeroext %c, <16 x i8> %x, <16 x i8> %y) {
%res = select i1 %c, <16 x i8> %x, <16 x i8> %y
ret <16 x i8> %res
}
Expand Down Expand Up @@ -99,7 +99,7 @@ define <8 x i16> @vselect_v8i16(<8 x i1> %c, <8 x i16> %x, <8 x i16> %y) {
; CHECK-NEXT: i16x8.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <8 x i16> @select_v8i16(i1 %c, <8 x i16> %x, <8 x i16> %y) {
define <8 x i16> @select_v8i16(i1 zeroext %c, <8 x i16> %x, <8 x i16> %y) {
%res = select i1 %c, <8 x i16> %x, <8 x i16> %y
ret <8 x i16> %res
}
Expand Down Expand Up @@ -170,7 +170,7 @@ define <4 x i32> @vselect_v4i32(<4 x i1> %c, <4 x i32> %x, <4 x i32> %y) {
; CHECK-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <4 x i32> @select_v4i32(i1 %c, <4 x i32> %x, <4 x i32> %y) {
define <4 x i32> @select_v4i32(i1 zeroext %c, <4 x i32> %x, <4 x i32> %y) {
%res = select i1 %c, <4 x i32> %x, <4 x i32> %y
ret <4 x i32> %res
}
Expand Down Expand Up @@ -240,7 +240,7 @@ define <2 x i64> @vselect_v2i64(<2 x i1> %c, <2 x i64> %x, <2 x i64> %y) {
; CHECK-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <2 x i64> @select_v2i64(i1 %c, <2 x i64> %x, <2 x i64> %y) {
define <2 x i64> @select_v2i64(i1 zeroext %c, <2 x i64> %x, <2 x i64> %y) {
%res = select i1 %c, <2 x i64> %x, <2 x i64> %y
ret <2 x i64> %res
}
Expand Down Expand Up @@ -313,7 +313,7 @@ define <4 x float> @vselect_v4f32(<4 x i1> %c, <4 x float> %x, <4 x float> %y) {
; CHECK-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <4 x float> @select_v4f32(i1 %c, <4 x float> %x, <4 x float> %y) {
define <4 x float> @select_v4f32(i1 zeroext %c, <4 x float> %x, <4 x float> %y) {
%res = select i1 %c, <4 x float> %x, <4 x float> %y
ret <4 x float> %res
}
Expand Down Expand Up @@ -383,7 +383,7 @@ define <2 x double> @vselect_v2f64(<2 x i1> %c, <2 x double> %x, <2 x double> %y
; CHECK-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <2 x double> @select_v2f64(i1 %c, <2 x double> %x, <2 x double> %y) {
define <2 x double> @select_v2f64(i1 zeroext %c, <2 x double> %x, <2 x double> %y) {
%res = select i1 %c, <2 x double> %x, <2 x double> %y
ret <2 x double> %res
}
Expand Down
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