use enumeration for flags

python · picnixz · Oct 5, 2024 · Oct 5, 2024 · Oct 5, 2024 · Oct 6, 2024
commit 553aa7c0460b9bce6e271c034122c765fcdce1c4
diff --git a/Include/internal/pycore_cpuinfo.h b/Include/internal/pycore_cpuinfo.h
@@ -23,6 +23,184 @@ extern "C" {
 
 #include "Python.h"
 
+/*
+ * The enumeration describes masks to apply on CPUID output registers.
+ *
+ * Member names are Py_CPUID_MASK_<REGISTER>_L<LEAF>[S<SUBLEAF>]_<FEATURE>,
+ * where <> (resp. []) denotes a required (resp. optional) group and:
+ *
+ * - REGISTER is EAX, EBX, ECX or EDX,
+ * - LEAF is the initial value of the EAX register (1 or 7),
+ * - SUBLEAF is the initial value of the ECX register (omitted if 0), and
+ * - FEATURE is a SIMD feature (with one or more specialized instructions).
+ *
+ * For maintainability, the flags are ordered by registers, leafs, subleafs,
+ * and bits. See https://en.wikipedia.org/wiki/CPUID for the values.
+ *
+ * Note 1: The LEAF is also called the 'page' or the 'level'.
+ * Note 2: The SUBLEAF is also referred to as the 'count'.
+ *
+ * The LEAF value should only 1 or 7 as other values may have different
+ * meanings depending on the underlying architecture.
+ */
+// fmt: off
+typedef enum py_cpuid_feature_mask {
+/*[python input]
+# {(LEAF, SUBLEAF, REGISTRY): {FEATURE: BIT}}
+data = {
+    (1, 0, 'ECX'): {
+        'SSE3': 0,
+        'PCLMULQDQ': 1,
+        'SSSE3': 9,
+        'FMA': 12,
+        'SSE4_1': 19,
+        'SSE4_2': 20,
+        'POPCNT': 23,
+        'XSAVE': 26,
+        'OSXSAVE': 27,
+        'AVX': 28,
+    },
+    (1, 0, 'EDX'): {
+        'CMOV': 15,
+        'SSE': 25,
+        'SSE2': 26,
+    },
+    (7, 0, 'EBX'): {
+        'AVX2': 5,
+        'AVX512_F': 16,
+        'AVX512_DQ': 17,
+        'AVX512_IFMA': 21,
+        'AVX512_PF': 26,
+        'AVX512_ER': 27,
+        'AVX512_CD': 28,
+        'AVX512_BW': 30,
+        'AVX512_VL': 31,
+    },
+    (7, 0, 'ECX'): {
+        'AVX512_VBMI': 1,
+        'AVX512_VBMI2': 6,
+        'AVX512_VNNI': 11,
+        'AVX512_BITALG': 12,
+        'AVX512_VPOPCNTDQ': 14,
+    },
+    (7, 0, 'EDX'): {
+        'AVX512_4VNNIW': 2,
+        'AVX512_4FMAPS': 3,
+        'AVX512_VP2INTERSECT': 8,
+    },
+    (7, 1, 'EAX'): {
+        'AVX_VNNI': 4,
+        'AVX_IFMA': 23,
+    },
+    (7, 1, 'EDX'): {
+        'AVX_VNNI_INT8': 4,
+        'AVX_NE_CONVERT': 5,
+        'AVX_VNNI_INT16': 10,
+    },
+}
+
+def get_member_name(leaf, subleaf, registry, name):
+    node = f'L{leaf}S{subleaf}' if subleaf else f'L{leaf}'
+    return f'Py_CPUID_MASK_{registry}_{node}_{name}'
+
+def get_member_mask(bit):
+    val = format(1 << bit, '008x')
+    return f'= 0x{val},'
+
+# BUG(picnixz): Clinic does not like when commented lines have empty lines.
+#               so we use '::' for now to indicate an empty line.
+# ::
+# The enumeration is rendered as follows:
+# ::
+#   <INDENT><MEMBER_NAME> <TAB>= 0x<MASK>, <TAB>// bit = BIT
+#   ^       ^             ^    ^   ^       ^    ^
+# ::
+# where ^ indicates a column that is a multiple of 4, <MASK> has
+# exactly 8 characters and <BIT> has at most 2 characters.
+
+INDENT = ' ' * 4
+# BUG(picnixz): Clinic does not like when '/' and '*' are put together.
+COMMENT = '/' + '* '
+
+def next_block(w):
+    """Compute the smallest multiple of 4 strictly larger than *w*."""
+    return ((w + 3) & ~0x03) if (w % 4) else (w + 4)
+
+NAMESIZE = next_block(max(
+    len(get_member_name(*group, name))
+    for group, values in data.items()
+    for name in values
+))
+MASKSIZE = 8 + next_block(len('= 0x,'))
+
+for group, values in data.items():
+    title = 'CPUID (LEAF={}, SUBLEAF={}) [{}]'.format(*group)
+    print(INDENT, *COMMENT, title, *COMMENT[::-1], sep='')
+    for name, bit in values.items():
+        assert name, f"invalid entry in {group}"
+        key = get_member_name(*group, name)
+        assert 0 <= bit < 32, f"invalid bit value for {name!r}"
+        val = get_member_mask(bit)
+
+        member_name = key.ljust(NAMESIZE)
+        member_mask = val.ljust(MASKSIZE)
+
+        print(INDENT, member_name, member_mask, f'// bit = {bit}', sep='')
+[python start generated code]*/
+    /* CPUID (LEAF=1, SUBLEAF=0) [ECX] */
+    Py_CPUID_MASK_ECX_L1_SSE3                   = 0x00000001,   // bit = 0
+    Py_CPUID_MASK_ECX_L1_PCLMULQDQ              = 0x00000002,   // bit = 1
+    Py_CPUID_MASK_ECX_L1_SSSE3                  = 0x00000200,   // bit = 9
+    Py_CPUID_MASK_ECX_L1_FMA                    = 0x00001000,   // bit = 12
+    Py_CPUID_MASK_ECX_L1_SSE4_1                 = 0x00080000,   // bit = 19
+    Py_CPUID_MASK_ECX_L1_SSE4_2                 = 0x00100000,   // bit = 20
+    Py_CPUID_MASK_ECX_L1_POPCNT                 = 0x00800000,   // bit = 23
+    Py_CPUID_MASK_ECX_L1_XSAVE                  = 0x04000000,   // bit = 26
+    Py_CPUID_MASK_ECX_L1_OSXSAVE                = 0x08000000,   // bit = 27
+    Py_CPUID_MASK_ECX_L1_AVX                    = 0x10000000,   // bit = 28
+    /* CPUID (LEAF=1, SUBLEAF=0) [EDX] */
+    Py_CPUID_MASK_EDX_L1_CMOV                   = 0x00008000,   // bit = 15
+    Py_CPUID_MASK_EDX_L1_SSE                    = 0x02000000,   // bit = 25
+    Py_CPUID_MASK_EDX_L1_SSE2                   = 0x04000000,   // bit = 26
+    /* CPUID (LEAF=7, SUBLEAF=0) [EBX] */
+    Py_CPUID_MASK_EBX_L7_AVX2                   = 0x00000020,   // bit = 5
+    Py_CPUID_MASK_EBX_L7_AVX512_F               = 0x00010000,   // bit = 16
+    Py_CPUID_MASK_EBX_L7_AVX512_DQ              = 0x00020000,   // bit = 17
+    Py_CPUID_MASK_EBX_L7_AVX512_IFMA            = 0x00200000,   // bit = 21
+    Py_CPUID_MASK_EBX_L7_AVX512_PF              = 0x04000000,   // bit = 26
+    Py_CPUID_MASK_EBX_L7_AVX512_ER              = 0x08000000,   // bit = 27
+    Py_CPUID_MASK_EBX_L7_AVX512_CD              = 0x10000000,   // bit = 28
+    Py_CPUID_MASK_EBX_L7_AVX512_BW              = 0x40000000,   // bit = 30
+    Py_CPUID_MASK_EBX_L7_AVX512_VL              = 0x80000000,   // bit = 31
+    /* CPUID (LEAF=7, SUBLEAF=0) [ECX] */
+    Py_CPUID_MASK_ECX_L7_AVX512_VBMI            = 0x00000002,   // bit = 1
+    Py_CPUID_MASK_ECX_L7_AVX512_VBMI2           = 0x00000040,   // bit = 6
+    Py_CPUID_MASK_ECX_L7_AVX512_VNNI            = 0x00000800,   // bit = 11
+    Py_CPUID_MASK_ECX_L7_AVX512_BITALG          = 0x00001000,   // bit = 12
+    Py_CPUID_MASK_ECX_L7_AVX512_VPOPCNTDQ       = 0x00004000,   // bit = 14
+    /* CPUID (LEAF=7, SUBLEAF=0) [EDX] */
+    Py_CPUID_MASK_EDX_L7_AVX512_4VNNIW          = 0x00000004,   // bit = 2
+    Py_CPUID_MASK_EDX_L7_AVX512_4FMAPS          = 0x00000008,   // bit = 3
+    Py_CPUID_MASK_EDX_L7_AVX512_VP2INTERSECT    = 0x00000100,   // bit = 8
+    /* CPUID (LEAF=7, SUBLEAF=1) [EAX] */
+    Py_CPUID_MASK_EAX_L7S1_AVX_VNNI             = 0x00000010,   // bit = 4
+    Py_CPUID_MASK_EAX_L7S1_AVX_IFMA             = 0x00800000,   // bit = 23
+    /* CPUID (LEAF=7, SUBLEAF=1) [EDX] */
+    Py_CPUID_MASK_EDX_L7S1_AVX_VNNI_INT8        = 0x00000010,   // bit = 4
+    Py_CPUID_MASK_EDX_L7S1_AVX_NE_CONVERT       = 0x00000020,   // bit = 5
+    Py_CPUID_MASK_EDX_L7S1_AVX_VNNI_INT16       = 0x00000400,   // bit = 10
+/*[python end generated code: output=e53c5376296af250 input=46c9e43c1f6f5cf9]*/
+} py_cpuid_feature_mask;
+// fmt: on
+
+/* XSAVE state components (XCR0 control register) */
+typedef enum py_xsave_feature_mask {
+    Py_XSAVE_MASK_XCR0_SSE              = 0x00000002,   // bit = 1
+    Py_XSAVE_MASK_XCR0_AVX              = 0x00000004,   // bit = 2
+    Py_XSAVE_MASK_XCR0_AVX512_OPMASK    = 0x00000020,   // bit = 5
+    Py_XSAVE_MASK_XCR0_AVX512_ZMM_HI256 = 0x00000040,   // bit = 6
+    Py_XSAVE_MASK_XCR0_AVX512_HI16_ZMM  = 0x00000080,   // bit = 7
+} py_xsave_feature_mask;
 
 typedef struct py_cpuid_features {
     uint32_t maxleaf;

diff --git a/Python/cpuinfo.c b/Python/cpuinfo.c
@@ -1,11 +1,11 @@
 #include "pycore_cpuinfo.h"
 
-#include <stdint.h>     // UINT32_C()
-
 /* CPUID input and output registers are 32-bit unsigned integers */
 #define CPUID_REG                   uint32_t
 /* Check one or more CPU
77F4
ID register bits. */
-#define CPUID_CHECK_REG(REG, MASK)  ((((REG) & (MASK)) == (MASK)) ? 0 : 1)
+#define CHECK_REG(REG, MASK)        ((((REG) & (MASK)) == (MASK)) ? 0 : 1)
+#define CPUID_CHECK_REG(REG, FEAT)  CHECK_REG(REG, (Py_CPUID_MASK_ ## FEAT))
+#define XSAVE_CHECK_REG(REG, FEAT)  CHECK_REG(REG, (Py_XSAVE_MASK_ ## FEAT))
 
 // For now, we only try to enable SIMD instructions for x86-64 Intel CPUs.
 // In the future, we should carefully enable support for ARM NEON and POWER
@@ -113,67 +113,6 @@
 #  define SHOULD_PARSE_CPUID_L7S1
 #endif
 
-/*
- * The macros below describe masks to apply on CPUID output registers.
- *
- * Each macro is of the form <REGISTER>_L<LEAF>[S<SUBLEAF>]_<FEATURE>,
- * where <> (resp. []) denotes a required (resp. optional) group and:
- *
- * - REGISTER is EAX, EBX, ECX or EDX,
- * - LEAF is the initial value of the EAX register (1 or 7),
- * - SUBLEAF is the initial value of the ECX register (omitted if 0), and
- * - FEATURE is a SIMD feature (with one or more specialized instructions).
- *
- * For maintainability, the flags are ordered by registers, leafs, subleafs,
- * and bits. See https://en.wikipedia.org/wiki/CPUID for the values.
- *
- * Note 1: The LEAF is also called the 'page' or the 'level'.
- * Note 2: The SUBLEAF is also referred to as the 'count'.
- */
-
-/* CPUID (LEAF=1, SUBLEAF=0) [ECX] */
-#define ECX_L1_SSE3                 (UINT32_C(1) << 0)  // 0x00000001
-#define ECX_L1_PCLMULQDQ            (UINT32_C(1) << 1)  // 0x00000002
-#define ECX_L1_SSSE3                (UINT32_C(1) << 9)  // 0x00000200
-#define ECX_L1_FMA                  (UINT32_C(1) << 12) // 0x00001000
-#define ECX_L1_SSE4_1               (UINT32_C(1) << 19) // 0x00080000
-#define ECX_L1_SSE4_2               (UINT32_C(1) << 20) // 0x00100000
-#define ECX_L1_POPCNT               (UINT32_C(1) << 23) // 0x00800000
-#define ECX_L1_XSAVE                (UINT32_C(1) << 26) // 0x04000000
-#define ECX_L1_OSXSAVE              (UINT32_C(1) << 27) // 0x08000000
-#define ECX_L1_AVX                  (UINT32_C(1) << 28) // 0x10000000
-/* CPUID (LEAF=1, SUBLEAF=0) [EDX] */
-#define EDX_L1_CMOV                 (UINT32_C(1) << 15) // 0x00008000
-#define EDX_L1_SSE                  (UINT32_C(1) << 25) // 0x02000000
-#define EDX_L1_SSE2                 (UINT32_C(1) << 26) // 0x04000000
-/* CPUID (LEAF=7, SUBLEAF=0) [EBX] */
-#define EBX_L7_AVX2                 (UINT32_C(1) << 5)  // 0x00000020
-#define EBX_L7_AVX512_F             (UINT32_C(1) << 16) // 0x00010000
-#define EBX_L7_AVX512_DQ            (UINT32_C(1) << 17) // 0x00020000
-#define EBX_L7_AVX512_IFMA          (UINT32_C(1) << 21) // 0x00200000
-#define EBX_L7_AVX512_PF            (UINT32_C(1) << 26) // 0x04000000
-#define EBX_L7_AVX512_ER            (UINT32_C(1) << 27) // 0x08000000
-#define EBX_L7_AVX512_CD            (UINT32_C(1) << 28) // 0x10000000
-#define EBX_L7_AVX512_BW            (UINT32_C(1) << 30) // 0x40000000
-#define EBX_L7_AVX512_VL            (UINT32_C(1) << 31) // 0x80000000
-/* CPUID (LEAF=7, SUBLEAF=0) [ECX] */
-#define ECX_L7_AVX512_VBMI          (UINT32_C(1) << 1)  // 0x00000002
-#define ECX_L7_AVX512_VBMI2         (UINT32_C(1) << 6)  // 0x00000040
-#define ECX_L7_AVX512_VNNI          (UINT32_C(1) << 11) // 0x00000800
-#define ECX_L7_AVX512_BITALG        (UINT32_C(1) << 12) // 0x00001000
-#define ECX_L7_AVX512_VPOPCNTDQ     (UINT32_C(1) << 14) // 0x00004000
-/* CPUID (LEAF=7, SUBLEAF=0) [EDX] */
-#define EDX_L7_AVX512_4VNNIW        (UINT32_C(1) << 2)  // 0x00000004
-#define EDX_L7_AVX512_4FMAPS        (UINT32_C(1) << 3)  // 0x00000008
-#define EDX_L7_AVX512_VP2INTERSECT  (UINT32_C(1) << 8)  // 0x00000100
-/* CPUID (LEAF=7, SUBLEAF=1) [EAX] */
-#define EAX_L7S1_AVX_VNNI           (UINT32_C(1) << 4)  // 0x00000010
-#define EAX_L7S1_AVX_IFMA           (UINT32_C(1) << 23) // 0x00800000
-/* CPUID (LEAF=7, SUBLEAF=1) [EDX] */
-#define EDX_L7S1_AVX_VNNI_INT8      (UINT32_C(1) << 4)  // 0x00000010
-#define EDX_L7S1_AVX_NE_CONVERT     (UINT32_C(1) << 5)  // 0x00000020
-#define EDX_L7S1_AVX_VNNI_INT16     (UINT32_C(1) << 10) // 0x00000400
-
 /*
  * Call __cpuid_count() or equivalent and get
  * its EAX, EBX, ECX and EDX output registers.
@@ -195,13 +134,6 @@
 #endif
 }
 
-/* XSAVE state components (XCR0 control register) */
-#define XCR0_SSE                    (UINT32_C(1) << 1)  // 0x00000002
-#define XCR0_AVX                    (UINT32_C(1) << 2)  // 0x00000004
-#define XCR0_AVX512_OPMASK          (UINT32_C(1) << 5)  // 0x00000020
-#define XCR0_AVX512_ZMM_HI256       (UINT32_C(1) << 6)  // 0x00000040
-#define XCR0_AVX512_HI16_ZMM        (UINT32_C(1) << 7)  // 0x00000080
-
 static inline uint64_t
 get_xgetbv(uint32_t index)
 {
@@ -380,11 +312,11 @@
     // Keep the ordering and newlines as they are declared in the structure.
 #ifdef HAS_XGETBV_SUPPORT
     uint64_t xcr0 = flags->osxsave ? get_xgetbv(0) : 0;
-    flags->xcr0_sse = CPUID_CHECK_REG(xcr0, XCR0_SSE);
-    flags->xcr0_avx = CPUID_CHECK_REG(xcr0, XCR0_AVX);
-    flags->xcr0_avx512_opmask = CPUID_CHECK_REG(xcr0, XCR0_AVX512_OPMASK);
-    flags->xcr0_avx512_zmm_hi256 = CPUID_CHECK_REG(xcr0, XCR0_AVX512_ZMM_HI256);
-    flags->xcr0_avx512_hi16_zmm = CPUID_CHECK_REG(xcr0, XCR0_AVX512_HI16_ZMM);
+    flags->xcr0_sse = XSAVE_CHECK_REG(xcr0, XCR0_SSE);
+    flags->xcr0_avx = XSAVE_CHECK_REG(xcr0, XCR0_AVX);
+    flags->xcr0_avx512_opmask = XSAVE_CHECK_REG(xcr0, XCR0_AVX512_OPMASK);
+    flags->xcr0_avx512_zmm_hi256 = XSAVE_CHECK_REG(xcr0, XCR0_AVX512_ZMM_HI256);
+    flags->xcr0_avx512_hi16_zmm = XSAVE_CHECK_REG(xcr0, XCR0_AVX512_HI16_ZMM);
 #endif
 }
 
@@ -392,7 +324,7 @@
 cpuid_features_finalize(py_cpuid_features *flags)
 {
    assert(flags->ready == 0);
    assert(flags->maxleaf >= 0);

    // Here, any flag that may depend on others should be correctly set
    // at runtime to avoid illegal instruction errors.