rp2: make GC lock work per CPU #7217
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This was referenced May 4, 2021
This commit makes gc_lock_depth have one counter per CPU core that the MicroPython VM can run on. This means a given core can run a hard IRQ independently to the other cores, ie only lock the GC for itself while the hard IRQ is running. The commit also changes protection of lock/unlock to use atomic state rather than a GC mutex (only enabled for GIL-less threading). This fixes a rare bug, on eg stm32, where a hard IRQ during a call to gc_lock() (eg 2 hard IRQs in quick succession, or a hard IRQ during a Python gc.lock() call) would put gc_lock_depth in a bad state. It also puts the check for gc_lock_depth outside the GC mutex in gc_alloc, gc_realloc and gc_free, to prevent a hard IRQ from waiting on a mutex. It also removes using the gc_lock during a collection: - scheduled code is not run - hard irqs should still be able to run - with GIL enabled, GIL is not released - with GIL disabled, other threads can continue to work until they need gc Signed-off-by: Damien George <damien@micropython.org>
So that hard IRQs can run correctly. Fixes issue micropython#6957. Signed-off-by: Damien George <damien@micropython.org>
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Closing in favour of #7238. |
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samd21: port_disable_tick() should disable event channel
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The rp2 port is the first port with multithreading without a GIL, and hard interrupts. To make such IRQs work correctly some things need to be improved wrt locking the GC.
This PR takes a first step by making
gc_lock_depthhave one instance per CPU core. That means that a given core can run a hard IRQ independently to the other, ie not lock the GC for the other CPU core while the hard IRQ is running.It also puts more code in RAM for the rp2 port to make
Pin.irq()have less jitter.Should fix #6957.