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ports/stm32/rfcore.c: STM32WB BLE improvements #6393
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@dmazzella FYI |
@jimmo tested and work for me. |
Rebased after merging #6405. Added RX IRQ handler. |
I think the only CI failure is black which wants to reformat |
The commit "Update rfcore.c to match ST examples." adds 2 commented-out lines that call LL_C2_EXTI_EnableEvent_32_63 and LL_EXTI_EnableRisingTrig_32_63, which are removed in commit "Minor refactoring.". Please remove them from the first commit there. |
- Split tables and buffers into SRAM2A/2B. - Use structs rather than word offsets to access tables. - Use FLASH_IPCCDBA register value rather than option bytes directly.
This is required to allow using WS firmware newer than 1.1.1 concurrently with USB (e.g. VCP). Prevents CPU2 from modifying the CLK48 config on boot. Tested on WS=1.8 FUS=1.1. See AN5289 and micropython#6316
Remove some magic numbers and explain the payload fixup code.
Before this change there was up to a 128ms delay on incoming payloads from CPU2 as it was polled by SysTick. Now the RX IRQ immediately schedules the PendSV.
fix SPI pin names qtpy esp32s3
Also some other minor fixes and tidy-ups.