8000 stm32/boards/NUCLEO_WB55: Add Python helper for rfcore. · micropython/micropython@5b9fbb4 · GitHub
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stm32/boards/NUCLEO_WB55: Add Python helper for rfcore.
This allows prototyping rfcore.c improvements from Python. This was mostly written by @dpgeorge with small modifications to work after rfcore_init() by @jimmo.
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‎ports/stm32/boards/NUCLEO_WB55/rfcore.py

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# This file is part of the MicroPython project, http://micropython.org/
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#
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# The MIT License (MIT)
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#
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# Copyright 8000 (c) 2020 Damien P. George
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# Copyright (c) 2020 Jim Mussared
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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# This script provides some helpers to allow Python code to access the IPCC
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# mechanism in the WB55, and works with the memory layout configured in
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# ports/stm32/rfcore.c -- i.e. it expects that rfcore_init() has been run.
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# At this stage this is useful for debugging, but can be extended to support
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# FUS/WS firmware updates.
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# e.g.
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# ../tools/pyboard.py --device /dev/ttyACM0 boards/NUCLEO_WB55/rfcore.py
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# to print out SRAM2A, register state and FUS/WS info.
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from machine import mem8, mem16, mem32
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import time, struct, uctypes
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import stm
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class Flash:
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FLASH_KEY1 = 0x45670123
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FLASH_KEY2 = 0xcdef89ab
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def wait_not_busy(self):
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while mem32[stm.FLASH + stm.FLASH_SR] & 1 << 16:
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machine.idle()
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def unlock(self):
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mem32[stm.FLASH + stm.FLASH_KEYR] = Flash.FLASH_KEY1
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mem32[stm.FLASH + stm.FLASH_KEYR] = Flash.FLASH_KEY2
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def lock(self):
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mem32[stm.FLASH + stm.FLASH_CR] = 1 << 31 # LOCK
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def erase_page(self, page):
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print('erase', page)
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assert 0 <= page <= 255 # 1MiB range (4k page)
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self.wait_not_busy()
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cr = (
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page << 3 # PNB
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| 1 << 1 # PER
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)
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mem32[stm.FLASH + stm.FLASH_CR] = cr
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mem32[stm.FLASH + stm.FLASH_CR] = cr | 1 << 16 # STRT
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self.wait_not_busy()
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mem32[stm.FLASH + stm.FLASH_CR] = 0
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def write(self, addr, buf):
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assert len(buf) % 4 == 0
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self.wait_not_busy()
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cr = (
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1 << 0 # PG
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)
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mem32[stm.FLASH + stm.FLASH_CR] = cr
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buf_addr = uctypes.addressof(buf)
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off = 0
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while off < len(buf):
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mem32[addr + off] = mem32[buf_addr + off]
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off += 4
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if off % 8 == 0:
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self.wait_not_busy()
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if off % 8:
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mem32[addr + off] = 0
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self.wait_not_busy()
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mem32[stm.FLASH + stm.FLASH_CR] = 0
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def copy_file_to_flash(filename, addr):
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flash = Flash()
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flash.unlock()
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try:
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with open(filename, 'rb') as f:
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buf = bytearray(4096)
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while 1:
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sz = f.readinto(buf)
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if sz == 0:
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break
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print('write', hex(addr), sz)
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flash.erase_page((addr - 0x08000000) // 4096)
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print('done e')
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flash.write(addr, buf)
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print('done')
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addr += 4096
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finally:
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flash.lock()
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SRAM2A_BASE = const(0x2003_0000)
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# for vendor OGF
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OGF_VENDOR = const(0x3f)
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OCF_FUS_GET_STATE = const(0x52)
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OCF_FUS_FW_UPGRADE = const(0x54)
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OCF_FUS_FW_DELETE = const(0x55)
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OCF_FUS_START_WS = const(0x5a)
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OCF_BLE_INIT = const(0x66)
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@micropython.asm_thumb
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def asm_sev_wfe():
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data(2, 0xbf40) # sev
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data(2, 0xbf20) # wfe
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TABLE_DEVICE_INFO = const(0)
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TABLE_BLE = const(1)
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TABLE_SYS = const(3)
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TABLE_MEM_MANAGER = const(4)
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CHANNEL_BLE = const(1)
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CHANNEL_SYS = const(2)
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CHANNEL_TRACES = const(4)
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CHANNEL_ACL = const(6)
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INDICATOR_HCI_COMMAND = const(0x01)
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INDICATOR_HCI_EVENT = const(0x04)
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INDICATOR_FUS_COMMAND = const(0x10)
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INDICATOR_FUS_RESPONSE = const(0x11)
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INDICATOR_FUS_EVENT = const(0x12)
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MAGIC_FUS_ACTIVE = const(0xa94656b9)
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def get_ipccdba():
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return mem32[stm.FLASH + stm.FLASH_IPCCBR] & 0x3fff
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def get_ipcc_table(table):
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return mem32[SRAM2A_BASE + get_ipccdba() + table * 4]
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def get_ipcc_table_word(table, offset):
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return mem32[get_ipcc_table(table) + offset * 4] & 0xffffffff
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def get_ipcc_table_byte(table, offset):
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return mem8[get_ipcc_table(table) + offset] & 0xff
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def sram2a_dump(num_words=64, width=8):
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print('SRAM2A @%08x' % SRAM2A_BASE)
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for i in range((num_words + width - 1) // width):
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print(' %04x ' % (i * 4 * width), end='')
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for j in range(width):
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print(' %08x' % (mem32[SRAM2A_BASE + (i * width + j) * 4] & 0xffffffff), end='')
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print()
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SYS_CMD_BUF = 0 # next*,prev*,type8,...; 272 bytes
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SYS_SYS_QUEUE = 0 # next*,prev*
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MM_BLE_SPARE_EVT_BUF = 0 # next*,prev*; 272 bytes
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MM_SYS_SPARE_EVT_BUF = 0 # next*,prev*; 272 bytes
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MM_BLE_POOL = 0 # ?
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MM_BLE_POOL_SIZE = 0 # ?
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MM_FREE_BUF_QUEUE = 0 # next*,prev*
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MM_EV_POOL = 0 # ?
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MM_EV_POOL_SIZE = 0 # ?
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BLE_CMD_BUF = 0
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BLE_CS_BUF = 0
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BLE_EVT_QUEUE = 0
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BLE_HCI_ACL_DATA_BUF = 0
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def ipcc_init():
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global SYS_CMD_BUF, SYS_SYS_QUEUE
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SYS_CMD_BUF = get_ipcc_table_word(TABLE_SYS, 0)
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SYS_SYS_QUEUE = get_ipcc_table_word(TABLE_SYS, 1)
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global MM_BLE_SPARE_EVT_BUF, MM_SYS_SPARE_EVT_BUF, MM_BLE_POOL, MM_BLE_POOL_SIZE, MM_FREE_BUF_QUEUE, MM_EV_POOL, MM_EV_POOL_SIZE
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MM_BLE_SPARE_EVT_BUF = get_ipcc_table_word(TABLE_MEM_MANAGER, 0)
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MM_SYS_SPARE_EVT_BUF = get_ipcc_table_word(TABLE_MEM_MANAGER, 1)
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MM_BLE_POOL = get_ipcc_table_word(TABLE_MEM_MANAGER, 2)
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MM_BLE_POOL_SIZE = get_ipcc_table_word(TABLE_MEM_MANAGER, 3)
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MM_FREE_BUF_QUEUE = get_ipcc_table_word(TABLE_MEM_MANAGER, 4)
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MM_EV_POOL = get_ipcc_table_word(TABLE_MEM_MANAGER, 5)
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MM_EV_POOL_SIZE = get_ipcc_table_word(TABLE_MEM_MANAGER, 6)
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global BLE_CMD_BUF, BLE_CS_BUF, BLE_EVT_QUEUE, BLE_HCI_ACL_DATA_BUF
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BLE_CMD_BUF = get_ipcc_table_word(TABLE_BLE, 0)
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BLE_CS_BUF = get_ipcc_table_word(TABLE_BLE, 1)
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BLE_EVT_QUEUE = get_ipcc_table_word(TABLE_BLE, 2)
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BLE_HCI_ACL_DATA_BUF = get_ipcc_table_word(TABLE_BLE, 3)
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print('IPCC initialised')
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print('SYS: 0x%08x 0x%08x' % (SYS_CMD_BUF, SYS_SYS_QUEUE))
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print('BLE: 0x%08x 0x%08x 0x%08x' % (BLE_CMD_BUF, BLE_CS_BUF, BLE_EVT_QUEUE))
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def tl_list_init(addr):
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mem32[addr] = addr # next
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mem32[addr + 4] = addr # prev
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def tl_list_append(head, n):
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sram2a_dump(1024)
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print('Appending 0x%08x to 0x%08x' % (head, n))
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# item->next = head
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mem32[n] = head
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# item->prev = head->prev
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mem32[n + 4] = mem32[head + 4]
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# head->prev->next = item
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mem32[mem32[head + 4]] = n
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# head->prev = item
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mem32[head + 4] = n
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def tl_list_unlink(n):
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# next = item->next
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next = mem32[n]
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# prev = item->prev
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prev = mem32[n + 4]
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# prev->next = item->next
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mem32[prev] = next
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# item->next->prev = prev
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mem32[next + 4] = prev
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return next
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def tl_list_dump(head):
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print('list(%08x, %08x, %08x):' % (head, mem32[head] & 0xffffffff, mem32[head + 4] & 0xffffffff), end='')
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cur = mem32[head]
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while cur != head:
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print(' %08x' % (cur & 0xffffffff), end='')
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cur = mem32[cur]
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print()
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def fus_active():
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return get_ipcc_table_word(TABLE_DEVICE_INFO, 0) == MAGIC_FUS_ACTIVE
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def info():
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sfr = mem32[stm.FLASH + stm.FLASH_SFR]
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srrvr = mem32[stm.FLASH + stm.FLASH_SRRVR]
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print('IPCCDBA : 0x%08x' % (get_ipccdba() & 0x3fff))
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print('DDS : %r' % bool(sfr & (1 << 12)))
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print('FSD : %r' % bool(sfr & (1 << 8)))
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print('SFSA : 0x%08x' % (sfr & 0xff))
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print('C2OPT : %r' % bool(srrvr & (1 << 31)))
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print('NBRSD : %r' % bool(srrvr & (1 << 30)))
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print('SNBRSA : 0x%08x' % ((srrvr >> 25) & 0x1f))
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print('BRSD : %r' % bool(srrvr & (1 << 23)))
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print('SBRSA : 0x%08x' % ((srrvr >> 18) & 0x1f))
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print('SBRV : 0x%08x' % (srrvr & 0x3ffff))
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def dev_info():
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def dump_version(offset):
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x = get_ipcc_table_word(TABLE_DEVICE_INFO, offset)
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print('0x%08x (%u.%u.%u.%u.%u)' % (x, x >> 24, x >> 16 & 0xff, x >> 8 & 0xff, x >> 4 & 0xf, x & 0xf))
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def dump_memory_size(offset):
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x = get_ipcc_table_word(TABLE_DEVICE_INFO, offset)
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print('0x%08x (SRAM2b=%uk SRAM2a=%uk flash=%uk)' % (x, x >> 24, x >> 16 & 0xff, (x & 0xff) * 4))
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print('Device information table @%08x:' % get_ipcc_table(TABLE_DEVICE_INFO))
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if fus_active():
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# layout when running FUS
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print('FUS is active')
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print('state : 0x%08x' % get_ipcc_table_word(TABLE_DEVICE_INFO, 0))
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print('last FUS active state : 0x%02x' % get_ipcc_table_byte(TABLE_DEVICE_INFO, 5))
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print('last wireless stack state: 0x%02x' % get_ipcc_table_byte(TABLE_DEVICE_INFO, 6))
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print('cur wireless stack type : 0x%02x' % get_ipcc_table_byte(TABLE_DEVICE_INFO, 7))
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print('safe boot version : ', end=''); dump_version(2)
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print('FUS version : ', end=''); dump_version(3)
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print('FUS memory size : ', end=''); dump_memory_size(4)
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print('wireless stack version : ', end=''); dump_version(5)
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print('wireless stack mem size : ', end=''); dump_memory_size(6)
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print('wireless FW-BLE info : 0x%08x' % get_ipcc_table_word(TABLE_DEVICE_INFO, 7))
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print('wireless FW-thread info : 0x%08x' % get_ipcc_table_word(TABLE_DEVICE_INFO, 8))
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print('UID64 : 0x%08x 0x%08x' % (get_ipcc_table_word(TABLE_DEVICE_INFO, 9), get_ipcc_table_word(TABLE_DEVICE_INFO, 10)))
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print('device ID : 0x%04x' % get_ipcc_table_word(TABLE_DEVICE_INFO, 11))
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else:
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# layout when running WS
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print('WS is active')
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print('safe boot version : ', end=''); dump_version(0)
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print('FUS version : ', end=''); dump_version(1)
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print('FUS memory size : ', end=''); dump_memory_size(2)
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print('FUS info : 0x%08x' % get_ipcc_table_word(TABLE_DEVICE_INFO, 3))
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print('wireless stack version : ', end=''); dump_version(4)
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print('wireless stack mem size : ', end=''); dump_memory_size(5)
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print('wireless stack info : 0x%08x' % get_ipcc_table_word(TABLE_DEVICE_INFO, 7))
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print('wireless reserved : 0x%08x' % get_ipcc_table_word(TABLE_DEVICE_INFO, 7))
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def ipcc_state():
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print('IPCC:')
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print(' C1CR: 0x%08x' % (mem32[stm.IPCC + stm.IPCC_C1CR] & 0xffffffff), end='')
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print(' C2CR: 0x%08x' % (mem32[stm.IPCC + stm.IPCC_C2CR] & 0xffffffff))
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print(' C1MR: 0x%08x' % (mem32[stm.IPCC + stm.IPCC_C1MR] & 0xffffffff), end='')
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print(' C2MR: 0x%08x' % (mem32[stm.IPCC + stm.IPCC_C2MR] & 0xffffffff))
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# these always read 0
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#print(' C1SCR: 0x%08x' % (mem32[stm.IPCC + stm.IPCC_C1SCR] & 0xffffffff), end='')
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#print(' C2SCR: 0x%08x' % (mem32[stm.IPCC + stm.IPCC_C2SCR] & 0xffffffff))
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print(' C1TOC2SR: 0x%08x' % (mem32[stm.IPCC + stm.IPCC_C1TOC2SR] & 0xffffffff), end='')
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print(' C2TOC1SR: 0x%08x' % (mem32[stm.IPCC + stm.IPCC_C2TOC1SR] & 0xffffffff))
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sram2a_dump(264)
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ipcc_init()
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info()
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dev_info()

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