STM32: Rework LSE clock init, allow clock overrides #3009
Conversation
There was a problem hiding this comment.
I concentrated on the parts relevant to the STM32F405 Feather and didn't see any problems.
I initially thought there was something functionally wrong about the code, because I merged it into my SDIO branch and got I/O errors. However, I am now seeing these I/O errors with the current tip of that PR's branch, so they do not seem to be due to this PR's changes after all.
|
Now overrides |
| #define HSE_VALUE ((uint32_t)25000000) | ||
| #define BOARD_OSC_PLLN (400) | ||
| #define BOARD_OSC_PLLQ (9) | ||
| // Lower frequency to allow external RAM use |
There was a problem hiding this comment.
Please explain this further. What clock needs to be lower to use external RAM? Why?
This PR significantly reworks the STM32 clock system, moving all LSE related settings to the peripherals directory, and streamlining clock settings across all development boards. Resolves a number of crashes that could occur across dev boards due to incorrect LSE setup, and adds LSE capability to the F7 and H7 chip families.
The restructuring of the clock system merges the clock setup of all SoCs in a family, reducing chip-line differences and defaults to macros only. Also introduces the ability for boards to override their frequency settings in the mpconfigboard.h profile, for cases where a user needs to reduce frequency operation to match a certain on-board peripheral or achieve better low-power performance.
Other changes:
Tested on: Feather F405, Discovery F412, Open MV H7, Nucleo F767. Any additional testing is greatly appreciated!
Resolves #2886
Resolves #3010
Older related temporary-fix PRs: #2866, #2979
Original low power PR: #2685