8000 lpc4322_hic: clock enhancements by groleo · Pull Request #925 · ARMmbed/DAPLink · GitHub
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lpc4322_hic: clock enhancements #925

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887c9fb
lpc43xx_hic: remove lpc43xx_cgu.{c|h}
Jan 9, 2022
5ea882a
lpc43xx_hic,uart: replace CGU code with direct register setup
Jan 9, 2022
f1315ba
lpc43xx_hic,system: extract N setup as ndec_new
Jan 9, 2022
ca753ed
lpc43xx_hic,system: extract P setup as pdec_new
Jan 9, 2022
abcbeec
lpc43xx_hic,system: extract M setup as mdec_new
Jan 9, 2022
dd0bb84
lpc43xx_hic,system: extract SELI setup as anadeci_new
Jan 9, 2022
cd0f4ae
lpc43xx_hic,system: extract SELI setup as anadecp_new
Jan 9, 2022
0885a2d
lpc43xx_hic,system: make use of WaitUs
Jan 9, 2022
a3e0b08
lpc43xx_hic,system: use defines where possible
Jan 9, 2022
3026c65
lpc43xx_hic,system: Enable USB0 PHY power
Jan 9, 2022
88d4bda
lpc43xx_hic,board: remove CGU code
Jan 9, 2022
422c5cc
lp43xx: use Driver_USART0 for virtual com port
Feb 15, 2022
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lpc43xx_hic,system: extract N setup as ndec_new
  • Loading branch information
Adrian Negreanu committed Feb 10, 2022
commit f1315ba65368ce1bf76eecd70a0c865ce5b0d1a7
30 changes: 17 additions & 13 deletions source/hic_hal/nxp/lpc4322/system_LPC43xx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -319,6 +319,22 @@ uint32_t GetClockFreq (uint32_t clk_src);
uint32_t SystemCoreClock = 120000000U; /* System Clock Frequency (Core Clock) */


#define PLL0_NSEL_MAX (1<<8)
/* pre-divider: compute ndec from nsel */
static unsigned ndec_new(unsigned nsel)
{
unsigned x=0x80, in;
switch (nsel)
{
case 0: return 0xFFFFFFFF;
case 1: return 0x302;
case 2: return 0x202;
default:
for (in = nsel; in <= PLL0_NSEL_MAX; in++)
x = ((x ^ x>>2 ^ x>>3 ^ x>>4) & 1) << 7 | x>>1 & 0xFF;
return x;
}
}
/******************************************************************************
* SetClock
******************************************************************************/
Expand Down Expand Up @@ -443,19 +459,7 @@ static void SetClock (void) {
(x << 0);

/* N divider */
x = 0x80;
switch (PLL0USB_N) {
case 0: x = 0xFFFFFFFF;
break;
case 1: x = 0x00000302;
break;
case 2: x = 0x00000202;
break;
default:
for (i = PLL0USB_N; i <= 0x0100; i++) {
x =(((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
}
}
x = ndec_new(PLL0USB_N);
LPC_CGU->PLL0USB_NP_DIV = (x << 12);

/* P divider */
Expand Down
0