8000 lpc4322_hic: clock enhancements by groleo · Pull Request #925 · ARMmbed/DAPLink · GitHub
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lpc4322_hic: clock enhancements #925

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887c9fb
lpc43xx_hic: remove lpc43xx_cgu.{c|h}
Jan 9, 2022
5ea882a
lpc43xx_hic,uart: replace CGU code with direct register setup
Jan 9, 2022
f1315ba
lpc43xx_hic,system: extract N setup as ndec_new
Jan 9, 2022
ca753ed
lpc43xx_hic,system: extract P setup as pdec_new
Jan 9, 2022
abcbeec
lpc43xx_hic,system: extract M setup as mdec_new
Jan 9, 2022
dd0bb84
lpc43xx_hic,system: extract SELI setup as anadeci_new
Jan 9, 2022
cd0f4ae
lpc43xx_hic,system: extract SELI setup as anadecp_new
Jan 9, 2022
0885a2d
lpc43xx_hic,system: make use of WaitUs
Jan 9, 2022
a3e0b08
lpc43xx_hic,system: use defines where possible
Jan 9, 2022
3026c65
lpc43xx_hic,system: Enable USB0 PHY power
Jan 9, 2022
88d4bda
lpc43xx_hic,board: remove CGU code
Jan 9, 2022
422c5cc
lp43xx: use Driver_USART0 for virtual com port
Feb 15, 2022
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lpc43xx_hic,system: make use of WaitUs
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Adrian Negreanu committed Feb 10, 2022
commit 0885a2ddbf959fe01926276e60f0bb118a9c0480
28 changes: 14 additions & 14 deletions source/hic_hal/nxp/lpc4322/system_LPC43xx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -319,6 +319,17 @@ uint32_t GetClockFreq (uint32_t clk_src);
uint32_t SystemCoreClock = 120000000U; /* System Clock Frequency (Core Clock) */


/*----------------------------------------------------------------------------
Approximate delay function (must be used after SystemCoreClockUpdate() call)
*----------------------------------------------------------------------------*/
static void WaitUs(uint32_t us, uint32_t clock_hz)
{
us *= (clock_hz / 1000000) / 3;

while (us--);
}


#define PLL0_NSEL_MAX (1<<8)
/* pre-divider: compute ndec from nsel */
static unsigned ndec_new(unsigned nsel)
Expand Down Expand Up @@ -417,7 +428,7 @@ static void SetClock (void) {
(0 << 2) ; /* Low-frequency mode */

/* Wait ~250us @ 12MHz */
for (i = 1500; i; i--);
WaitUs(250, CLK_XTAL);

#ifdef USE_SPIFI
/* configure SPIFI clk to IRC via IDIVA (later IDIVA is configured to PLL1/3) */
Expand Down Expand Up @@ -456,8 +467,8 @@ static void SetClock (void) {
LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
(0x09 << 24) ; /* Clock source: PLL1 */

/* Max. BASE_M4_CLK frequency here is 102MHz, wait at least 20us */
for (i = 1050; i; i--); /* Wait minimum 2100 cycles */
/* Wait 20us */
WaitUs(20, (CLK_XTAL * (PLL1_MSEL + 1)) / ((PLL1_NSEL + 1) * 2));
#endif
/* Configure PLL1 */
LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */
Expand Down Expand Up @@ -547,17 +558,6 @@ static void SetClock (void) {
}


/*----------------------------------------------------------------------------
Approximate delay function (must be used after SystemCoreClockUpdate() call)
*----------------------------------------------------------------------------*/
#define CPU_NANOSEC(x) (((uint64_t)(x) * SystemCoreClock)/1000000000)

static void WaitUs (uint32_t us) {
uint32_t cyc = us * CPU_NANOSEC(1000)/4;
while(cyc--);
}


/*----------------------------------------------------------------------------
Measure frequency using frequency monitor
*----------------------------------------------------------------------------*/
Expand Down
0