[go: up one dir, main page]
Next Article in Journal
Measuring Uncertainty Analysis of the New Leveling Staff Calibration System
Next Article in Special Issue
N-Channel MOSFET Reliability Issue Induced by Visible/Near-Infrared Photons in Image Sensors
Previous Article in Journal
Mutual Coupling Reduction of a Multiple-Input Multiple-Output Antenna Using an Absorber Wall and a Combline Filter for V2X Communication
Previous Article in Special Issue
Evaluation of Microlenses, Color Filters, and Polarizing Filters in CIS for Space Applications
 
 
Search for Articles:
Title / Keyword
Author / Affiliation / Email
Journal
Article Type
 
 
Advanced Search
 
Section
Special Issue
Volume
Issue
Number
Page
 
Journals
Sensors
Volume 23
Issue 14
10.3390/s23146356
sensors-logo
Submit to this Journal Review for this Journal Propose a Special Issue
► Article Menu

Article Menu

share Share announcement Help format_quote Cite question_answer Discuss in SciProfiles thumb_up
...
Endorse textsms
...
Comment
first_page
settings
Order Article Reprints
Font Type:
Arial Georgia Verdana
Font Size:
Aa Aa Aa
Line Spacing:
Column Width:
Background:
Article

Design and Characterization of a Burst Mode 20 Mfps Low Noise CMOS Image Sensor

by
Xin Yue
* and
Eric R. Fossum
Thayer School of Engineering at Dartmouth, Dartmouth College, Hanover, NH 03755, USA
*
Author to whom correspondence should be addressed.
Sensors 2023, 23(14), 6356; https://doi.org/10.3390/s23146356
Submission received: 27 June 2023 / Revised: 10 July 2023 / Accepted: 10 July 2023 / Published: 13 July 2023
(This article belongs to the Special Issue Recent Advances in CMOS Image Sensor)
Browse Figures
Figure 1
<p>(<b>a</b>) Simplified cross-section of a narrow PPD. (<b>b</b>) Electrostatic potential along the red-dashed line.</p> "> Figure 2
<p>(<b>a</b>) Photodiode finger shapes with different electric fields. (<b>b</b>) Conceptual layout of a pixel with a built-in 900 V/cm electric filed.</p> "> Figure 3
<p>Electrostatic potential along the charge transfer path for various photodiode designs.</p> "> Figure 4
<p>(<b>a</b>) Conceptual layout of the proposed high-speed pixel. (<b>b</b>) Operation timing of a charge-sweep-gate based pixel.</p> "> Figure 5
<p>TCAD 3D model of the proposed pixel with expanded view.</p> "> Figure 6
<p>Electrostatic potential plots along the charge transfer path during charge transfer.</p> "> Figure 7
<p>TCAD transient simulation result of the proposed pixel.</p> "> Figure 8
<p>(<b>a</b>) Schematic of the proposed high-speed pixel. (<b>b</b>) Capacitance distribution at FD node.</p> "> Figure 9
<p>(<b>a</b>) 3D TCAD model of the default buried channel NMOS and its cross-section. (<b>b</b>) 3D TCAD model of the proposed buried channel NMOS and its cross-section.</p> "> Figure 10
<p>DC sweep simulation results of buried channel NMOSs.</p> "> Figure 11
<p>In-pixel CDS circuit.</p> "> Figure 12
<p>(<b>a</b>) schematic and (<b>b</b>) layout of in-pixel storage unit.</p> "> Figure 13
<p>Complete pixel schematic with 108 sample-and-hold capacitors.</p> "> Figure 14
<p>(<b>a</b>) The microscopic image of the designed image sensor chip. (<b>b</b>) The protype test system.</p> "> Figure 15
<p>(<b>a</b>) Test setup for video capturing. (<b>b</b>) LED array and its driver circuit. (<b>c</b>) Images captured by the sensor at 400 Kfps. LEDS are on for frames 1–6 and off for remaining frames.</p> ">
Review Reports Versions Notes

Abstract

:
This paper presents a novel ultra-high speed, high conversion-gain, low noise CMOS image sensor (CIS) based on charge-sweep transfer gates implemented in a standard 180 nm CIS process. Through the optimization of the photodiode geometry and the utilization of charge-sweep transfer gates, the proposed pixels achieve a charge transfer time of less than 10 ns without requiring any process modifications. Moreover, the gate structure significantly reduces the floating diffusion capacitance, resulting in an increased conversion gain of 183 µV/e−. This advancement enables the image sensor to achieve the lowest reported noise of 5.1 e− rms. To demonstrate the effectiveness of both optimizations, a proof-of-concept CMOS image sensor is designed, taped-out and characterized.

1. Introduction

Ultra-high-speed (UHS) image sensors find extensive application in various fields, including medical, scientific, and industrial domains, enabling visualization and understanding of UHS phenomena. Several recent studies [1,2,3,4,5,6,7,8] have successfully achieved frame rates of up to hundreds of millions of frames per second (Mfps) for these specialized sensors. However, these achievements rely heavily on advanced processes, such as 130 nm backside illumination (BSI)-Charge-Coupled Device (CCD) or customized processes tailored specifically for this application. Unfortunately, these advanced/customized processes often come with prohibitively high costs or limited accessibility due to resource constraints. Therefore, there is a pressing need to improve process compatibility. Additionally, the published works commonly encounter relatively high noise due to the inherent trade-off between the design requirement for quick readout speed (favoring smaller capacitance) and the need for lower thermal noise (requiring larger capacitance). Wu et al. [6] reported the lowest state-of-the-art input-referred noise to be 8.4 e− rms.
This paper presents a methodology for optimizing the charge transfer time, conversion gain and read noise by introducing the concept of charge-sweep transfer gates. We demonstrate the feasibility of these techniques by implementing them using a standard 180 nm FSI non-stacked process in a 64 × 64-pixel array. Through simulation and characterization, we show that the designed CMOS image sensor has the potential to achieve a frame rate of 20 Mfps and an input-referred noise of 5.1 e− rms. Use of these techniques in an advanced 3D-stacked BSI process in the future would lead to further improvements of speed, fill factor, and pixel layout efficiency.
The paper is organized as follows: First, the approach to designing the photodiode and transfer gates is described. Next, the circuitry for in-pixel correlated double sampling (CDS) and the memory array is presented. Then, the sensor noise is calculated and simulated. Finally, characterization results are provided and the discrepancy between simulation and characterization is analyzed.

2. Pixel Core Design

Pixel pitch for high-speed image sensors is larger than for most consumer image sensors in order to increase light gathering for very short integration times. Collections of photoelectrons across larger pixels can take longer than for smaller pixels. It is widely known that there are two main mechanisms for carrier transport in semiconductors [9]: diffusion current, resulting from concentration gradients, and drift current, caused by the presence of an electric field. Electrons can achieve significantly higher velocity in a strong electric field, leading to shorter charge transfer times attributed to drift current compared to diffusion current. Hence, the crucial factor for achieving ultra-high-speed pixels lies in the successful implementation of a strong electric field within the photodiode for fast carrier collection.
In modern pinned photodiodes (PPD) [7,10], the p+ layer deposited on top of the n region plays a crucial role in pinning the surface potential and reducing dark current, depleting the free electrons in the photodiode, and reducing image lag. Analytical studies by Krymski and Feklistov [11] and Park and Uh [12] have pointed out that the maximum electrostatic potential is influenced by the photodiode width, especially for small-size pixels, due to 3D photodiode effects. Figure 1a illustrates a simplified cross-section of a narrow-pinned photodiode. When considering 3D photodiode effects, for a fully depleted n-region, the electrostatic potential along the red-dashed line can be plotted in Figure 1b. This potential is described by Equation (1) [13], which provides a simplified relationship between the maximum electrostatic potential (ψmax) in the photodiode, the elementary charge (q), the effective doping concentration of the photodiode (ND), the doping concentration of the substrate (NA), and the photodiode’s half-width (xn).
ψ m a x ≈ q · N D ⋅ x n 2 2 ⋅ ε 0 ⋅ ε r 1 + N D N A
A more advanced 2D model that accounts for the impact of all four PN junctions in a pinned photodiode is available in Liu et al. [14]. However, for quick analysis of the electric field, the simplified 1D model is sufficient. By adjusting the photodiode’s width along its length, it is possible to establish a consistently strong electric field within the photodiode, as shown by Equation (2). In this equation, x and y denote the coordinates of the photodiode’s envelope, E represents the constant electric field, and C0 stands for a constant.
y = − q ⋅ N D ⋅ x 2 2 ⋅ E ⋅ ε 0 ⋅ ε r 1 + N D N A + C 0
Assuming a medium doping concentration at room temperature and an electron mobility of 1500 cm2/Vs [15], and considering a charge transfer time that does not exceed 2.5 ns based on system-level calculations, a minimum constant electrical field is calculated to be 370 V/cm. In order to accommodate process variation and the potential occurrence of high dark currents caused by strong electrical fields [16], the electric field within the photodiode along the charge transfer direction ranges from 400 V/cm to 900 V/cm. This results in different photodiode geometric shapes, labeled E400 to E900, as depicted in Figure 2a.
Figure 2b illustrates a conceptual pixel layout that is based on the E900 photodiode depicted in Figure 2a. Through calculations, the photodiode will have a built-in electric field of 900 V/cm. In order to accelerate the simulation process, this simple pixel model only consists of the photodiode (PD), transfer gate (TX), floating diffusion node (FD), reset gate (RST), and reset drain (VDD). The electrostatic potential within the photodiode along the charge transfer path and the charge transfer time, for different photodiode designs, are simulated using Technology Computer-Aided Design (TCAD), and the corresponding results can be found in Figure 3 and Table 1. Simulation results show a stronger electric field than the simple estimation based on Equation (2). This discrepancy may be attributed to the 3D effect of the pinned photodiode.
In this design, a criterion of 0.5% charge transfer inefficiency (CTI) was selected to ensure satisfactory image lag performance. Considering the system-level requirements, the TX pulse width, including control signal rising and falling time, must be limited to 10 ns. Consequently, only the E700, E800, and E900 designs, as highlighted, meet the criteria. After evaluating the accommodations involving dark current, fill-factor, and process variation, the E800 design was ultimately selected as the high-speed photodiode design in this paper.
Inspired by the pixel designs presented in Suzuki et al. and Cao et al [1,17] and CCD in CMOS [18,19,20], we propose a high-speed pixel design and introduce the concept of charge-sweep transfer gates, as illustrated in Figure 4a. Each photodiode finger in this pixel is identical to the E800 design shown in Figure 2a, albeit with a rotated angle. Unlike the conventional 4T pixel, our design incorporates TX3, TX2, and TX1 gates to establish a strong electrical field pointing from the tip of the photodiode to the center of the pixel, enabling quick charge transfer. The operational timing of this pixel is depicted in Figure 4b. During the beginning of the charge transfer, all three gates, TX1, TX2, and TX3, are simultaneously turned on. Notably, the voltage of TX1 is higher than that of TX2, and the voltage of TX2 is higher than that of TX3. Upon completion of the charge transfer, the TX3 gate is turned off first, followed by TX2, and finally TX1, sequentially sweeping electrons from TX3 to FD.
In order to accurately simulate the device, the proposed pixel is also modeled in TCAD, as depicted in Figure 5. For the sake of clarity, the silicon dioxide (SiO2) layer that fully covers the entire pixel is not displayed, but TX1, TX2, TX3, RST, SF, SEL, and their respective metal connections are visible. Figure 6 illustrates electrostatic potential plots along the charge transfer path in one PD under various TX voltages on the red-dashed cut-plane. The plot clearly shows the presence of a small potential barrier (~0.1 V) between two adjacent gates due to the gap between gates. By controlling the falling edge slew rate of the TX gates, it is possible to eliminate the potential barrier during the falling transition of the TX gates. This process establishes a monotonically increasing electrostatic potential profile and generates a strong electrical field that sweeps previously stored electrons to the next gate, ultimately enabling a full charge transfer.
A TCAD transient simulation was conducted to verify the complete charge transfer of the proposed design. The results are illustrated in Figure 7, where eTotal1 and eTotal2 represent the total number of electrons in the upper and lower photodiodes, respectively. At the start of the charge transfer process, there are 111 and 92 electrons in the two photodiodes, respectively. Within 10 ns, both eTotal1 and eTotal2 rapidly decrease to less than 1 electron, indicating successful full charge transfer. Following the charge transfer operation, the FD voltage changes from 2.366145 V to 2.338567 V, resulting in a Conversion Gain (CG) of 136 μV/e−.
As mentioned previously, high-speed CMOS image sensors are prone to relatively high noise due to the trade-off between design requirements for fast readout speed and lower thermal noise. In order to tackle this issue, a passive correlated double sampling (CDS) amplifier was proposed by Wu et al. [6] to reduce input-referred noise. However, the gain of the passive CDS amplifier relies on the capacitance ratio between the NMOS capacitor in depletion mode and inversion mode, which is dependent on both the process and voltage. Consequently, this introduces an unavoidable non-linearity to the entire image sensor, approximately at a level of 3% [6]. Furthermore, the settling of the amplified voltage imposes limitations on the frame rate.
Therefore, in this design, the image sensor’s CG was proposed to be improved to minimize input-referred noise. Figure 8a illustrates the schematic of the proposed pixel, highlighting the major capacitance contribution, while Figure 8b displays the capacitance distribution at FD of the pixel, with the dominant factors being the FD-to-ground capacitance (Cfd_gnd) and the FD-to-Source Follower Drain capacitor (Csfd_fd), leaving potential for further optimization.
Figure 9a illustrates a 3D TCAD model showing the default minimal buried channel NMOS in this process, along with its cross-section. It is evident that the effective channel length is significantly shorter than the gate length due to the diffusion of n dopants in the source and drain, impeding the reduction of the transistor gate length. Directly reducing the gate length beyond the design rule limit can potentially lead to an increased leakage current between the drain and source, primarily due to drain-induced barrier lowering (DIBL). Moreover, this reduction may induce other short channel effects or even cause a direct short circuit. Based on the ideas presented in Kusuhara et al. and Seo et al. [21,22], we propose the elimination of the lightly-doped-drain (LDD) at the drain side, enabling further transistor shrinkage and reduction of FD capacitance. Figure 9b illustrates this proposed modification, which involves only mask changes.
To determine the optimal NMOS transistor design, we explore the gap distance ranging from 0 µm to 0.3 µm. Both the proposed buried channel NMOS transistor (L = 0.3 µm, gap = 0 µm~0.3 µm) and the default transistor (L = 0.6 µm, gap = 0 µm) are configured as a source follower biased with an ideal DC current sink. The gate voltage was swept from 1.5 V to 2.5 V and the corresponding results are plotted in Figure 10. It is clear that designs with L = 0.3 µm, Gap = 0 µm; L = 0.3 µm, Gap = 0.1 µm; and L = 0.6 µm, Gap = 0 µm demonstrate superior linearity compared to the other designs.
As discussed earlier, eliminating the LDD region results in a notable decrease in the overlap capacitance between the gate and drain. Table 2 presents the Cgd values along with other alternating current (AC) parameters for different design configurations.
Taking into account the Miller effect, the design with L = 0.3 and Gap = 0.1 achieves the smallest lumped capacitance at FD. Consequently, this design will be employed in the high CG version of the proposed pixel.
Concerns may arise regarding the increased flicker noise caused by smaller gate geometries. As mentioned in Boukhayma et al. [23], the smaller SF gate enhances the conversion gain and reduces input-referred noise, particularly when a fast CDS circuit is utilized. Another concern might be the potential occurrence of the hot electron effect in the absence of lightly doped drain (LDD) regions. However, as shown in Figure 9b, a “lightly doped” region still exists on the drain side due to the diffusion effect, and being physically separated from the channel. Therefore, in terms of electrical field, the proposed new design exhibits a lower peak electric field compared to the default design under the same bias conditions. Consequently, the proposed new design presents a lower probability of high-energy collisions than the default design.
A TCAD transient simulation is conducted again to validate the efficiency of the proposed source follower. The transient simulation demonstrates a significant increase in CG, from 136 μV/e− to 178 μV/e−.This result closely aligns with the findings from the previous AC simulation.
To distinguish between these two pixels throughout the remainder of this paper, the pixel with the default source follower will be referred to as the baseline pixel, while the pixel employing the proposed source follower will be referred to as the HCG (high conversion gain) pixel.

3. In-Pixel CDS and Memory Bank

In most CMOS image sensors, input-referred noise is primarily dominated by in-pixel SF thermal and flicker noise. To mitigate low-frequency noise originating from the pixel source follower, pixel reset kTC noise, and fixed-pattern noise (FPN), we have implemented the correlated-double-sampling (CDS) circuit [24] shown in Figure 11 for this project. To minimize voltage gain attenuation in the signal chain, we have positioned the sample-and-hold capacitor (CSH) at the output of the first-stage source-follower, contrary to its placement at the input of the second-stage source-follower, as described in Miyauchi et al. [25]. This arrangement effectively reduces voltage attenuation in the signal chain to CCDS/(CCDS + CP), where CCDS represents the AC CDS capacitor and CP represents the parasitic capacitor. Its operation timing is shown in Figure 4b.
According to the design requirements, each pixel requires at least 100 sample-and-hold capacitors. To increase the capacitance density, a custom Metal-1 (M1) Metal-Oxide-Metal (MOM) capacitor is placed on the top of the 1.8 V thin poly gate of the NMOS capacitor. Moreover, a Metal-2 (M2) layer is utilized as a shielding layer positioned above the M1 MOM capacitor, as depicted in Figure 12. To protect the 1.8 V thin gate devices in a 3.3 V environment, the VRST voltage is isolated from VDDpix and can be independently adjusted. Typically, the VRST voltage is set to 1.8 + VGS_SF2 to ensure that the maximum output voltage of SF2 remains below 1.8 V.
With this design, a total of 108 units of sample and hold capacitors, each having a capacitance of 78 fF, can be accommodated within a 52.8 µm pixel in the final layout. To reduce the capacitance loading of source follower SF2 and minimize possible charge corruption, a capacitor bank with a hierarchical switches network and individual controls is used. The schematic of the final pixel is illustrated in Figure 13.

4. Sensor Noise Estimation

Despite the high pixel conversion gain designed for this image sensor, it is still crucial to meticulously analyze the noise of the signal chain. The primary noise sources within this sensor have been identified and highlighted in red in Figure 13.
Contributor 1 represents the flicker noise and thermal noise originating from the in-pixel 1st stage source follower (SF1). A thorough measurement and validation of the flicker noise model were performed by Deng and Fossum [26] for Taiwan Semiconductor Manufacturing Company (TSMC) processes, revealing that the Hooge mobility fluctuation model matches the experimental measurements best. Even though a different process is used in this design, the model can still be used for quick calculation. Equation (3) displays the normalized power spectrum density (PSD) of the flicker noise, as presented in Deng and Fossum [26], where αH stands for Hooge’s parameter and Cox refers to the oxide capacitance per unit area. Equation (4) describes the classical thermal noise spectrum of SFs, where gm denotes the transconductance of the source follower, r is the excess noise factor, and k is Boltzmann’s constant.
s I b _ f l i c k e r f I b 2 = α H f × 2 q C o x W L × ( V G S − V t h )
s I b _ t h e r m a l f = 4 k T r g m
Given the limited bandwidth of SFs, the transfer function of the in-pixel 1st SF can be treated as a low-pass filter. This behavior is depicted by Equation (5), where fc denotes the cutoff frequency.
H L P 1 f = 1 1 + f ∕ f c 2
Therefore, the total noise voltage produced by contributor 1 at its output can be obtained by consolidating Equations (3)–(5), as shown in Equation (6). In this equation, ASF represents the gain of the source follower and Δ t stands for the time difference between pixel reset votlage sampling and pixel signal votlage sampling in CDS operations.
V n 1 2 = ∫ 0 ∞ s I b 1 _ t h e r m a l f + s I b 1 _ f l i c k e r f g m 1 2 × A S F 1 2 × H L P 1 f 2 × ( 2 × sin ⁡ π f Δ t ) 2
Contributor 2 denotes the kTC noise arising from the Brownian motion of carriers within the RST2 switch. As per classical theory, the kTC voltage noise is determined by Equation (7), where C denotes the capacitance of the CDS capacitor.
V n 2 2 = k T C
Contributor 3 represents the flicker noise and thermal noise generated by the in-pixel 2nd-stage source follower (SF2). It is worth noting that a relatively larger transistor size is required to reduce the flicker noise, given the absence of CDS noise cancellation. Its overall noise contribution, as depicted in Equation (8), is similar to that of contributor 1.
V n 3 2 = ∫ 0 ∞ s I b 2 _ t h e r m a l f + s I b 2 _ f l i c k e r f g m 2 2 × A S F 2 2 × H L P 2 f 2
Contributor 4 represents the kTC noise from the sample-and-hold switch. Similar to contributor 2, the voltage noise can be obtained by Equation (9), where CSH stands for the capacitance of the sample-and-hold capacitor.
V n 4 2 = k T C S H
Contributor 5 represents the kTC noise from the RST3 switch, which will be attenuated by the sample-and-hold capacitor. The total equivalent noise can be calculated by Equation (10).
V n 5 2 = k T C p a r a 2 × ( C p a r a 2 C p a r a 2 + C S H ) 2
Contributor 6 denotes the flicker noise and thermal noise that arise from the in-pixel 3rd-stage source follower (SF3). Similar to contributor 3, the cumulative noise at the output can be determined using Equation (11).
V n 6 2 = ∫ 0 ∞ s I b 3 _ t h e r m a l f + s I b 3 _ f l i c k e r f g m 3 2 × A S F 3 2 × H L P 3 f 2
Contributor 7 denotes the thermal noise originating from the column output buffer (not shown in the figure), which is a simple 5 transistors operational transconductance amplifier (OTA). Considering the comparatively larger size of the input pair, its flicker noise component is negligible. The overall output noise of the buffer can be determined by Equation (12).
V n 7 2 = 2 4 k T r g m 1 + 4 k T r g m 2 × R o u t 2 × B W 2
Therefore, the total output voltage noise of the whole image sensor can be estimated by Equation (13). It is crucial to note that, for the sake of quick calculation, any additional bandwidth limiting caused by subsequent stages has been disregarded in this simple calculation. The variables used in this equation include ACDS, which represents the attenuation introduced by the CDS capacitor, ASF2, the low frequency gain of the 2nd-stage source follower, ASH, the attenuation introduced by the sample-and-hold capacitor and Cpara2, ASF3, the low frequency gain of the 3rd-stage source follower, and AUGB, the low frequency gain of the column output buffer.
V n o u t p u t 2 = V n 1 2 × A C D S 2 × A S F 2 2 × A S H 2 × A S F 3 2 × A U G B 2         + V n 2 2 × A S F 2 2 × A S H 2 × A S F 3 2 × A U G B 2 + V n 3 2 × A S H 2 × A S F 3 2 × A U G B 2         + V n 4 2 × A S F 3 2 × A U G B 2 + V n 5 2 × A S F 3 2 × A U G B 2 + V n 6 2 × A U G B 2         + V n 7 2
The Spectre AC noise simulation is used for quick noise estimation. Table 3 shows the simulated values for Vn1 to Vn7 and the gain of each stage. According to the simulation results and Equation (13), the estimated output-referred noise at the pad is 414 µV root-mean-square (rms), while the input-referred noise at the FD node is 5.8 e−, assuming that the CG is 136 µV/e− for a baseline pixel.
The noise of the high-conversion gain (HCG) version is also estimated. Although a Simulation Program with Integrated Circuit Emphasis (SPICE) model for the proposed source follower is unavailable, it is still possible to estimate the flicker noise and thermal contribution based on Equations (3) and (4). Table 4 presents the total noise values for the HCG pixel. According to the simulation results, the output-referred noise at the pad is 418 µV rms, while the input-referred noise at the FD node is 4.6 e−, assuming that the CG is 178 µV/e− for a baseline pixel.

5. Characterization

The sensor was fabricated in a standard 180 nm PPD process. Figure 14 displays the microscopic image of the designed sensor and its prototype testing system. In this version, three types of pixels were taped out. Baseline pixels (64 pix × 32 pix) are positioned on the left side of the pixel array, HCG pixels (32 pix × 32 pix) are located on the upper right of the pixel array, and test pixels (32 pix × 32 pix) are situated on the bottom right of the pixel array, as indicated in Figure 14a.
Although TCAD simulations have demonstrated the sensor’s capability to operate at a minimum of 20 Mfps [27], the current prototype camera system faces limitations due to the hardware capabilities of the Field Programmable Gate Arrays (FPGA), prototype Printed circuit board (PCB), and chip carrier. These constraints impose a maximum reliable operation of 15.6 Mfps. Moreover, the parasitic inductances of the chip carrier introduce substantial ringing on the power supply VRST during pixel reset operations and prolong the CDS time. As a result, to achieve optimal noise performance, the imager noise is currently measured at 4 Mfps.
It is important to mention that conventional image sensors typically measure noise in completely dark conditions to minimize the impact of photon shot noise. However, in the case of this ultra-high-speed image sensor, the contribution of both photon shot noise and dark current must be taken into account. Therefore, during noise measurement, the TX1 voltage is kept low (“off”). The measured data reveals that the output-referred noise at the pad is 10.9 DN for baseline pixels, corresponding to 415 µV, and 12.0 DN for HCG pixels, corresponding to 457 µV. Here, 1 DN is equal to 38 µV. These voltage noise values closely align with the initial estimations reported in Table 3 and Table 4.
For photon transfer curve (PTC) measurement, to mitigate the impact of dark current, which can result in inaccurate CG measurements, a powerful light source is used, and the integration times are deliberately kept relatively low. The measured result yields PTC slopes of 0.41 and 0.50 for the baseline pixel and HCG pixels, respectively, in the region dominated by photon shot noise. These values are in close proximity to the ideal value of 0.5. Consequently, it is reliable to determine the pixel CG under this setup. After being adjusted by the signal chain gain of 0.485 V/V, the calculated baseline pixel CG is found to be 98 µV/e− and the HCG pixel CG is found to be 183 µV/e−. Therefore, the sensor’s input-referred noise was determined to be 8.7 e− for the baseline pixel and 5.1 e− for the HCG pixel.
Based on the same setup, we measured the full well capacity (FWC) of two pixels as well. The measured data shows that baseline pixel output reaches saturation at approximately 8500 DN, equivalent to 6800 e−, and the HCG pixel output saturates at around 11,600 DN, corresponding to 5000 e−.
At 300 K, the baseline pixel shows a dark electron rate at 0.66 e−/ns/pixel, whereas the HCG pixel exhibits 0.46 e−/ns/pixel. The measured results exceed the expected values and current evidence suggests a higher than anticipated trap state density in the silicon bulk. According to the classical Shockley-Read-Hall recombination (SRH) theory [28,29,30], reducing the temperature can decrease the dark current rate. At 256 K, both the baseline pixel and the HCG pixel exhibit a dark electron rate of less than 0.01 e−/ns/pixel. For the intended application, where the frame rate is 20 Mfps, the maximum theoretically possible integration time is 50 ns. Consequently, the maximum number of dark electrons is only 0.5, significantly smaller than the sensor’s noise floor.
The sensor is specifically designed to capture ultra-high-speed events occurring within microseconds while maintaining minimal image lag. Currently limited by the speed of the testing light source, the sensor was slowed down to 142 Kfps to perform the lag test, with the pixel TX3 pulse duration fixed at 10 ns. Based on the measurement results, the baseline pixel exhibits a negligible lag of 0.03%. On the other hand, the HCG pixel shows a lag of approximately 3% due to overflow at the floating diffusion node. However, by adjusting the TX gate’s negative off voltage, it was possible to mitigate the lag.
Figure 15a illustrates the test setup, with a camera lens mounted on the PCB to demonstrate a video capturing the falling edge of a focused LED array, where LEDs were on for the first six frames and stayed off for the remaining frames. Figure 15b shows the image of an LED array and its hand-made driver circuit. Figure 15c exhibits the captured video, comprised of 108 frames. It is important to note that the LED array has a limited light intensity. Therefore, to collect enough photons per frame, the image sensor needs to slow down to 400 Kfps for this test. The captured images show non-uniformity, which is caused by LED non-uniformity.

6. Conclusions

This paper presents the design and characterization of an ultra-high-speed burst-mode low-noise CMOS image sensor. The most challenging aspect of the design is implementing it in a standard 180 nm PPD process. Overcoming this challenge involves achieving full charge transfer within 10 ns and minimizing floating diffusion capacitance without making any process modifications. To do so, the concept of process-independent charge-sweep transfer gate was invented and optimized. The simulation and measurement results demonstrate an acceptable match in terms of noise, pixel conversion gain, and charge transfer time. Table 5 summarizes the sensor characterization results and Table 6 shows a comparison of this work to related state-of-the-art sensors.
Demonstrated performance of the sensor, while consistent with simulation and modeling, was limited by both the use of an off-the-shelf package and by the brightness of the test system modulated light sources. An improved packaging and test system environment can be explored in the future.

Author Contributions

Conceptualization, designing, analysis, validation, writing—original draft, review and editing, X.Y.; supervision and review, E.R.F. All authors have read and agreed to the published version of the manuscript.

Funding

This research received funding from Los Alamos National Laboratory and Department of Energy.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

Data available on request.

Acknowledgments

The author would like to thank Xuezhou Cao, Stephanie Wee, Jifeng Liu, Kofi Odame, Rihito Kuroda, Jeph Wang, Bob Reinovsky, Guang Yang, and Xiaomu Lan and Jiaju Ma for their enlightening discussions and encouragement.

Conflicts of Interest

The authors declare no conflict of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript; or in the decision to publish the results.

References

  1. Suzuki, M.; Sugama, Y.; Kuroda, R.; Sugawa, S. Over 100 Million Frames per Second 368 Frames Global Shutter Burst CMOS Image Sensor with Pixel-wise Trench Capacitor Memory Array. Sensors 2020, 20, 1086. [Google Scholar] [CrossRef] [Green Version]
  2. Tochigi, Y.; Hanzawa, K.; Kato, Y.; Kuroda, R.; Mutoh, H.; Hirose, R.; Tominaga, H.; Takubo, K.; Kondo, Y.; Sugawa, S. A Global-Shutter CMOS Image Sensor with Readout Speed of 1-Tpixel/s Burst and 780-Mpixel/s Continuous. IEEE J. Solid-State Circuits 2013, 48, 329–338. [Google Scholar] [CrossRef]
  3. Suzuki, M.; Kuroda, R.; Kumagai, Y.; Chiba, A.; Miura, N.; Kuriyama, N.; Sugawa, S. An over 1Mfps global shutter CMOS image sensor with 480 frame storage using vertical analog memory integration. In Proceedings of the 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 3–7 December 2016; IEEE Xplore: Piscataway, NJ, USA, 2016. [Google Scholar]
  4. Dao, V.T.S.; Ngo, N.; Nguyen, A.Q.; Morimoto, K.; Shimonomura, K.; Goetschalckx, P.; Haspeslagh, L.; De Moor, P.; Takehara, K.; Etoh, T.G. An Image Signal Accumulation Multi-Collection-Gate Image Sensor Operating at 25 Mfps with 32 × 32 Pixels and 1220 In-Pixel Frame Memory. Sensors 2018, 18, 3112. [Google Scholar] [CrossRef] [Green Version]
  5. Etoh, T.G.; Okinaka, T.; Takano, Y.; Takehara, K.; Nakano, H.; Shimonomura, K.; Ando, T.; Ngo, N.; Kamakura, Y.; Dao, V.T.S.; et al. Light-In-Flight Imaging by a Silicon Image Sensor: Toward the Theoretical Highest Frame Rate. Sensors 2019, 19, 2247. [Google Scholar] [CrossRef] [PubMed] [Green Version]
  6. Wu, L.; Bello, D.S.S.; Coppejans, P.; Craninckx, J.; Süss, A.; Rosmeulen, M.; Wambacq, P.; Borremans, J. Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification. Sensors 2018, 18, 3683. [Google Scholar] [CrossRef] [PubMed] [Green Version]
  7. Kagawa, K.; Horio, M.; Pham, A.N.; Ibrahim, T.; Okihara, S.-I.; Furuhashi, T.; Takasawa, T.; Yasutomi, K.; Kawahito, S.; Nagahara, H. A Dual-Mode 303-Megaframes-per-Second Charge-Domain Time-Compressive Computational CMOS Image Sensor. Sensors 2022, 22, 1953. [Google Scholar] [CrossRef] [PubMed]
  8. Mochizuki, F.; Kagawa, K.; Okihara, S.-I.; Seo, M.-W.; Zhang, B.; Takasawa, T.; Yasutomi, K.; Kawahito, S. Single-event transient imaging with an ultra-high-speed temporally compressive multi-aperture CMOS image sensor. Opt. Express 2016, 24, 4155–4176. [Google Scholar] [CrossRef] [PubMed]
  9. Theuwissen, A.J. Solid-State Imaging with Charge-Coupled Devices; Springer Science & Business Media: Dordrecht, The Netherlands, 2006; pp. 27–31. [Google Scholar]
  10. Fossum, E.R.; Hondongwa, D.B. A review of the pinned photodiode for CCD and CMOS image sensors. IEEE J. Electron Devices Soc. 2014, 2, 33–43. [Google Scholar] [CrossRef]
  11. Krymski, A.; Feklistov, K. Estimates for scaling of pinned photodiodes. In Proceedings of the 2005 IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors, Nagano, Japan, 9–11 June 2005; pp. 60–63. [Google Scholar]
  12. Park, S.; Uh, H. The effect of size on photodiode pinch-off voltage for small pixel CMOS image sensors. Microelectron. J. 2009, 40, 137–140. [Google Scholar] [CrossRef]
  13. Takeshita, H.; Sawada, T.; Iida, T.; Yasutomi, K.; Kawahito, S. High-speed charge transfer pinned-photodiode for a CMOS time-of-flight range image sensor. In Proceedings of the IS&T/SPIE Electronic Imaging, San Jose, CA, USA, 17–21 January 2010. [Google Scholar]
  14. Liu, L.; Yang, S.; Yan, M.; Li, B.; Guo, Y.; Guo, M.; Li, G.; Zhou, E. The effect of photodiode shape on pinning potential for charge transfer in CMOS image sensors. Microelectron. J. 2023, 131, 105651. [Google Scholar] [CrossRef]
  15. Streetman, B.G.; Banerjee, S.K. Solid State Electronic Devices, 6th ed.; Prentice Hall: Boston, MA, USA, 2016; p. 105. [Google Scholar]
  16. Roy, K.; Mukhopadhyay, S.; Mahmoodi-Meimand, H. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc. IEEE 2003, 91, 305–327. [Google Scholar] [CrossRef]
  17. Cao, X.; Gäbler, D.; Lee, C.; Ling, T.P.; Jarau, D.A.; Tien, D.K.C.; Chuan, T.B.; Bold, B. Design and optimisation of large 4T pixel. In Proceedings of the 2015 International Image Sensor Workshop (IISW), Vaals, The Netherlands, 8–11 June 2015; pp. 112–115. Available online: https://www.imagesensors.org/Past%20Workshops/2015%20Workshop/2015%20Papers/Sessions/Session_5-Posters1/5-08_X-CAO.pdf (accessed on 15 June 2023).
  18. Marcelot, O.; Estribeau, M.; Goiffon, V.; Martin-Gonthier, P.; Corbiere, F.; Molina, R.; Rolando, S.; Magnan, P. Study of CCD Transport on CMOS Imaging Technology: Comparison Between SCCD and BCCD, and Ramp Effect on the CTI. IEEE Trans. Electron Devices 2014, 61, 844–849. [Google Scholar] [CrossRef] [Green Version]
  19. Borg, J.; Johansson, J. Evaluation of a Surface-Channel CCD Manufactured in a Pinned Active-Pixel-Sensor CMOS Process. IEEE Trans. Electron Devices 2011, 58, 2660–2664. [Google Scholar] [CrossRef]
  20. Stefanov, K.D.; Prest, M.J.; Downing, M.; George, E.; Bezawada, N.; Holland, A.D. Simulations and Design of a Single-Photon CMOS Imaging Pixel Using Multiple Non-Destructive Signal Sampling. Sensors 2020, 20, 2031. [Google Scholar] [CrossRef] [PubMed] [Green Version]
  21. Kusuhara, F.; Wakashima, S.; Nasuno, S.; Kuroda, R.; Sugawa, S. Analysis and reduction technologies of floating diffusion capacitance in CMOS image sensor for photon-countable sensitivity. ITE Trans. Media Technol. Appl. 2016, 4, 91–98. [Google Scholar] [CrossRef] [Green Version]
  22. Seo, M.-W.; Kawahito, S.; Kagawa, K.; Yasutomi, K. A 0.27e-rms Read Noise 220-μV/e-Conversion Gain Reset-Gate-Less CMOS Image Sensor with 0.11-μm CIS Process. IEEE Electron Device Lett. 2015, 36, 1344–1347. [Google Scholar] [CrossRef]
  23. Boukhayma, A.; Kraxner, A.; Caizzone, A.; Yang, M.; Bold, D.; Enz, C. Comparison of Two in Pixel Source Follower Schemes for Deep Subelectron Noise CMOS Image Sensors. IEEE J. Electron Devices Soc. 2022, 10, 687–695. [Google Scholar] [CrossRef]
  24. De Wit, Y.; Walschap, T.; Cremers, B. In-Pixel Correlated Double Sampling Pixel. U.S. Patent 12/766,798, 28 October 2010. [Google Scholar]
  25. Miyauchi, K.; Takeda, T.; Hanzawa, K.; Tochigi, Y.; Sakai, S.; Kuroda, R.; Tominaga, H.; Hirose, R.; Takubo, K.; Kondo, Y.; et al. Pixel structure with 10 nsec fully charge transfer time for the 20m frame per second burst CMOS image sensor. In Proceedings of the 2014 IS&T/SPIE Electronic Imaging, San Francisco, CA, USA, 2–6 February 2014; NASA ADS: Cambridge, MA, USA, 2014; Volume 9022, p. 902203. [Google Scholar] [CrossRef]
  26. Deng, W.; Fossum, E.R. 1/f Noise Modelling and Characterization for CMOS Quanta Image Sensors. Sensors 2019, 19, 5459. [Google Scholar] [CrossRef] [PubMed] [Green Version]
  27. Yue, X.; Fossum, E.R. Simulation and design of a burst mode 20Mfps global shutter high conversion gain CMOS image sensor in a standard 180nm CMOS image sensor process using sequential transfer gates. Electron. Imaging 2023, 35, 328-1–328-5. [Google Scholar] [CrossRef]
  28. Teranishi, N. Dark current and white blemish in image sensors. In Proceedings of the 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Hsinchu, Taiwan, 22–24 April 2013; IEEE Xplore: Piscataway, NJ, USA, 2013. Available online: https://ieeexplore.ieee.org/document/6545639 (accessed on 4 May 2023).
  29. Shockley, W.; Read, W.T. Statistics of the Recombinations of Holes and Electrons. Phys. Rev. 1952, 87, 835–842. [Google Scholar] [CrossRef]
  30. Liu, E. The Physics of Semiconductors, 7th ed.; Publishing House of Electronics Industry: Beijing, China, 2017; pp. 131–135. [Google Scholar]
  31. Millet, L.; Vigier, M.; Sicard, G.; Uhring, W.; Margotat, N.; Guellec, F.; Martin, S. A 5 Million Frames Per Second 3D Stacked Image Sensor with In-Pixel Digital Storage. In Proceedings of the ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC), Dresden, Germany, 3–6 September 2018; IEEE: Piscataway, NJ, USA, 2018; pp. 62–65. [Google Scholar]
Sensors 23 06356 g001 550
Figure 1. (a) Simplified cross-section of a narrow PPD. (b) Electrostatic potential along the red-dashed line.
Figure 1. (a) Simplified cross-section of a narrow PPD. (b) Electrostatic potential along the red-dashed line.
Sensors 23 06356 g001
Sensors 23 06356 g002 550
Figure 2. (a) Photodiode finger shapes with different electric fields. (b) Conceptual layout of a pixel with a built-in 900 V/cm electric filed.
Figure 2. (a) Photodiode finger shapes with different electric fields. (b) Conceptual layout of a pixel with a built-in 900 V/cm electric filed.
Sensors 23 06356 g002
Sensors 23 06356 g003 550
Figure 3. Electrostatic potential along the charge transfer path for various photodiode designs.
Figure 3. Electrostatic potential along the charge transfer path for various photodiode designs.
Sensors 23 06356 g003
Sensors 23 06356 g004 550
Figure 4. (a) Conceptual layout of the proposed high-speed pixel. (b) Operation timing of a charge-sweep-gate based pixel.
Figure 4. (a) Conceptual layout of the proposed high-speed pixel. (b) Operation timing of a charge-sweep-gate based pixel.
Sensors 23 06356 g004
Sensors 23 06356 g005 550
Figure 5. TCAD 3D model of the proposed pixel with expanded view.
Figure 5. TCAD 3D model of the proposed pixel with expanded view.
Sensors 23 06356 g005
Sensors 23 06356 g006 550
Figure 6. Electrostatic potential plots along the charge transfer path during charge transfer.
Figure 6. Electrostatic potential plots along the charge transfer path during charge transfer.
Sensors 23 06356 g006
Sensors 23 06356 g007 550
Figure 7. TCAD transient simulation result of the proposed pixel.
Figure 7. TCAD transient simulation result of the proposed pixel.
Sensors 23 06356 g007
Sensors 23 06356 g008 550
Figure 8. (a) Schematic of the proposed high-speed pixel. (b) Capacitance distribution at FD node.
Figure 8. (a) Schematic of the proposed high-speed pixel. (b) Capacitance distribution at FD node.
Sensors 23 06356 g008
Sensors 23 06356 g009 550
Figure 9. (a) 3D TCAD model of the default buried channel NMOS and its cross-section. (b) 3D TCAD model of the proposed buried channel NMOS and its cross-section.
Figure 9. (a) 3D TCAD model of the default buried channel NMOS and its cross-section. (b) 3D TCAD model of the proposed buried channel NMOS and its cross-section.
Sensors 23 06356 g009
Sensors 23 06356 g010 550
Figure 10. DC sweep simulation results of buried channel NMOSs.
Figure 10. DC sweep simulation results of buried channel NMOSs.
Sensors 23 06356 g010
Sensors 23 06356 g011 550
Figure 11. In-pixel CDS circuit.
Figure 11. In-pixel CDS circuit.
Sensors 23 06356 g011
Sensors 23 06356 g012 550
Figure 12. (a) schematic and (b) layout of in-pixel storage unit.
Figure 12. (a) schematic and (b) layout of in-pixel storage unit.
Sensors 23 06356 g012
Sensors 23 06356 g013 550
Figure 13. Complete pixel schematic with 108 sample-and-hold capacitors.
Figure 13. Complete pixel schematic with 108 sample-and-hold capacitors.
Sensors 23 06356 g013
Sensors 23 06356 g014 550
Figure 14. (a) The microscopic image of the designed image sensor chip. (b) The protype test system.
Figure 14. (a) The microscopic image of the designed image sensor chip. (b) The protype test system.
Sensors 23 06356 g014
Sensors 23 06356 g015 550
Figure 15. (a) Test setup for video capturing. (b) LED array and its driver circuit. (c) Images captured by the sensor at 400 Kfps. LEDS are on for frames 1–6 and off for remaining frames.
Figure 15. (a) Test setup for video capturing. (b) LED array and its driver circuit. (c) Images captured by the sensor at 400 Kfps. LEDS are on for frames 1–6 and off for remaining frames.
Sensors 23 06356 g015
Table
Table 1. Charge Transfer Time Simulation Results of Different Designs.
Table 1. Charge Transfer Time Simulation Results of Different Designs.
CTI10%1%0.5%0.1%Unit
E40010.241.251.375.2ns
E5000.617.425.847.0ns
E6000.65.011.028.3ns
E7000.71.55.119.3ns
E8000.81.13.715.5ns
E9000.91.33.613.6ns
Table
Table 2. AC Performance of Different SF Designs.
Table 2. AC Performance of Different SF Designs.
SF Length (µm)Gap Dist. (µm)Gain@Vg = 2.5 V (V/V)Gain@Vg = 1.5 V (V/V)Cgs (fF)Cgd (fF)
0.30.00.820.770.520.22
0.30.10.870.850.570.17
0.30.20.830.880.660.15
0.30.30.470.680.680.12
0.60.00.890.890.790.26
Table
Table 3. Sensor noise estimation based on a baseline pixel.
Table 3. Sensor noise estimation based on a baseline pixel.
Noise SourceCap Size
(pF)		Stage Noise
(µV)		Stage Gain
(V/V)		Noise Contribution
(µV2)		Noise Percentage
(%)		Total Noise
(µV)
1. 1st-Stg SF 3740.81213,19333
2. Rst2 kTC0.0802330.9682,81913
3. 2nd-Stg SF 1910.9074,48512
4. S/H kTC0.0782360.78113,78818
5. Rst3 kTC 1691.0095,84915
6. 3rd-Stg SF 0950.8938,23706
7. Out Buffer 0821.0028,48804
Noise @ FD 804
Noise @ Pad 414
Table
Table 4. Sensor noise estimation based on HCG pixel.
Table 4. Sensor noise estimation based on HCG pixel.
Noise SourceCap Size
(pF)		Stage Noise
(µV)		Stage Gain
(V/V)		Noise Contribution
(µV2)		Noise Percentage
(%)		Total Noise
(µV)
1. 1st-Stg SF 3850.81225,91834
2. Rst2 kTC0.0802330.9682,81913
3. 2nd-Stg SF 1910.9074,48511
4. S/H kTC0.0782360.78113,78817
5. Rst3 kTC 1691.0095,84915
6. 3rd-Stg SF 0950.8938,23706
7. Out Buffer 0821.0028,48804
Noise @ FD 812
Noise @ Pad 418
Table
Table 5. Sensor Characteristics Summary.
Table 5. Sensor Characteristics Summary.
Sensor Characteristics Summary
Process180 nm standard PPD CISUnit
Pixel Pitch52.8 × 52.8µm × µm
Pixel Fill Factor9.7%
Pixel Array Size64 × 64pix × pix
Recording Length108frames
Pixel VariantBaselineHCG
Measurement/SimulationMesa.Sim.Meas.Sim.
Charge Transfer Time≤10≤10≤10≤10ns
Conversion Gain98136183178µV/e−
Output-Referred Noise415414457418µV
Input-Referred Noise8.75.85.14.6e−
Image Lag≤0.1≤0.5≤3≤0.1%
FWC6.07.05.05.6Ke−
Low Light Linearity±0.5±0.2±0.5±0.2%
Dark Current (300 K)6.9 × 10−11.6 × 10−44.6 × 10−11.6 × 10−4e−/ns/pixel
Dark Current (256 K)1.0 × 10−2N/A9.2 × 10−3N/Ae−/ns/pixel
Table
Table 6. Performance Comparison with recently published high speed image sensors.
Table 6. Performance Comparison with recently published high speed image sensors.
Ref.Node
(nm)		Process
Modi?		Array (H × V)Pitch
(µm)		CG
(µV/e−)		FWC (Ke−)Frame Rate (Mfps)Record LengthNoise
(e−)
[1]180 FSIYes50 × 108359911100368N/R
[2]180 FSIYes400 × 2563274N/R10128N/R
[3]180 FSIYes96 × 128321121010480N/R
[4]130 BSIYes32 × 3272.5N/RN/R251220N/R
[5]130 CCDYes512 × 57512.7N/R71005N/R
[6]130 BSIN/R32 × 84301056201088.4
[7]110 FSIYes212 × 18822.432333031285
[8]110 FSIYes320 × 32411.2N/R1020015>167
[31]90 + 40N/R20 × 20507.3137552>81
This work180 FSINo64 × 6452.81835201085.1
Disclaimer/Publisher’s Note: The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of MDPI and/or the editor(s). MDPI and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content.

Share and Cite

MDPI and ACS Style

Yue, X.; Fossum, E.R. Design and Characterization of a Burst Mode 20 Mfps Low Noise CMOS Image Sensor. Sensors 2023, 23, 6356. https://doi.org/10.3390/s23146356

AMA Style

Yue X, Fossum ER. Design and Characterization of a Burst Mode 20 Mfps Low Noise CMOS Image Sensor. Sensors. 2023; 23(14):6356. https://doi.org/10.3390/s23146356

Chicago/Turabian Style

Yue, Xin, and Eric R. Fossum. 2023. "Design and Characterization of a Burst Mode 20 Mfps Low Noise CMOS Image Sensor" Sensors 23, no. 14: 6356. https://doi.org/10.3390/s23146356

Note that from the first issue of 2016, this journal uses article numbers instead of page numbers. See further details here.

Article Metrics

Back to TopTop