Design an All-Optical Combinational Logic Circuits Based on Nano-Ring Insulator-Metal-Insulator Plasmonic Waveguides
<p>The proposed structure for the proposed plasmonic four combinational logic functions.</p> "> Figure 2
<p>(<b>a</b>,<b>b</b>) the conventional half-adder logic diagram and its truth table, respectively. (<b>c</b>) The transmission spectrum of the proposed plasmonic half-adder for different states, according to its truth table. (<b>d</b>,<b>e</b>) the magnetic field distribution of Logic 00 and Logic 11 inputs, respectively.</p> "> Figure 3
<p>(<b>a</b>,<b>b</b>) the conventional half-subtractor logic diagram and its truth table, respectively. (<b>c</b>) The transmission spectrum of the proposed plasmonic half-subtractor for different states, according to its truth table. (<b>d</b>,<b>e</b>) the magnetic field distribution of Logic 10 and Logic 11 inputs, respectively.</p> "> Figure 4
<p>(<b>a</b>) and (<b>b</b>) the conventional comparator one-bit logic diagram and its truth table, respectively. (<b>c</b>) The transmission spectrum of the proposed plasmonic comparator one-bit for different states, according to its truth table. (<b>d</b>), (<b>e</b>), (<b>f</b>) and (<b>g</b>) the magnetic field distribution of Logic 00, 01, 10, and 11 inputs, respectively.</p> "> Figure 5
<p>(<b>a</b>) and (<b>b</b>) the conventional full-adder logic symbol and its truth table, respectively. (<b>c</b>) The transmission spectrum of the proposed plasmonic full-adder for different states, according to its truth table. (<b>d</b>), (<b>e</b>), (<b>f</b>) and (<b>g</b>) the magnetic field distribution of Logic 001, 011, 110, and 111 inputs, respectively.</p> ">
Abstract
:1. Introduction
2. Structure Layout and Theoretical Concept
3. The Proposed All-Optical Combinational Logic Functions
3.1. Plasmonic Half-Adder Combinational Logic Circuit
3.2. Plasmonic Half-Subtractor Combinational Logic Circuit
3.3. Plasmonic Comparator One-Bit Combinational Logic Circuit
3.4. Plasmonic Full-Adder Combinational Logic Circuit
4. The Comparison between the Proposed Work and the Previous Works
5. Conclusions
Author Contributions
Funding
Conflicts of Interest
References
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Input | Input | Input 1 | Input 2 | Input 1 | Input 2 |
---|---|---|---|---|---|
State 1 | State 2 | Port 1 | Port 2 | Port 5 | Port 6 |
(Phase) | (Phase) | (Phase) | (Phase) | ||
Logic 0 | Logic 0 | OFF (0) | OFF (0) | OFF (0) | OFF (0) |
Logic 0 | Logic 1 | OFF (0) | ON (0) | OFF (0) | ON (0) |
Logic 1 | Logic 0 | ON (0) | OFF (0) | ON (0) | OFF (0) |
Logic 1 | Logic 1 | ON (45) | ON (180) | ON (0) | ON (0) |
Control | Control | T (Port 4) | T (Port 7) | Tthresh | Sum | Output | Output | Output |
---|---|---|---|---|---|---|---|---|
Port 3 | Port 8 | Output | Carry | Port 4 | Port 7 | |||
(Phase) | (Phase) | |||||||
ON (0) | ON (0) | 0.07 | 0.07 | 0.25 | Logic 0 | Logic 0 | OFF | OFF |
ON (0) | ON (0) | 0.62 | 0.06 | 0.25 | Logic 1 | Logic 0 | ON | OFF |
ON (0) | ON (0) | 0.63 | 0.06 | 0.25 | Logic 1 | Logic 0 | ON | OFF |
ON (0) | ON (0) | 0.05 | 0.72 | 0.25 | Logic 0 | Logic 1 | OFF | ON |
Input | Input | Input 1 | Input 2 | Input 1 | Input 2 |
---|---|---|---|---|---|
State 1 | State 2 | Port 1 | Port 2 | Port 5 | Port 6 |
(Phase) | (Phase) | (Phase) | (Phase) | ||
Logic 0 | Logic 0 | OFF (0) | OFF (0) | OFF (0) | OFF (0) |
Logic 0 | Logic 1 | OFF (0) | ON (0) | OFF (0) | ON (0) |
Logic 1 | Logic 0 | ON (0) | OFF (0) | ON (180) | OFF (0) |
Logic 1 | Logic 1 | ON (45) | ON (180) | ON (180) | ON (45) |
Control | Control | T (Port 4) | T (Port 8) | Tthresh | D | Borrow | Output | Output |
---|---|---|---|---|---|---|---|---|
Port 3 | Port 8 | Output | Carry | Port 4 | Port 8 | |||
(Phase) | (Phase) | |||||||
ON (0) | ON (0) | 0.07 | 0.07 | 0.25 | Logic 0 | Logic 0 | OFF | OFF |
ON (0) | ON (0) | 0.62 | 0.63 | 0.25 | Logic 1 | Logic 1 | ON | ON |
ON (0) | ON (0) | 0.63 | 0.18 | 0.25 | Logic 1 | Logic 0 | ON | OFF |
ON (0) | ON (0) | 0.05 | 0.05 | 0.25 | Logic 0 | Logic 0 | OFF | OFF |
Input | Input | Input 1 | Input 2 | Input 1 | Input 2 | Control | Control |
---|---|---|---|---|---|---|---|
State 1 | State 2 | Port 2 | Port 3 | Port 5 | Port 6 | Port 1 | Port 7 |
(Phase) | (Phase) | (Phase) | (Phase) | (Phase) | (Phase) | ||
Logic 0 | Logic 0 | OFF (0) | OFF (0) | OFF (0) | OFF (0) | ON (180) | ON (0) |
Logic 0 | Logic 1 | OFF (0) | ON (0) | OFF (0) | ON (0) | ON (180) | ON (0) |
Logic 1 | Logic 0 | ON (0) | OFF (0) | ON (180) | OFF (0) | ON (180) | ON (0) |
Logic 1 | Logic 1 | ON (45) | ON (180) | ON (180) | ON (45) | ON (180) | ON (0) |
T (Port 4) | T (Port 8) | Tthresh | A = B | A > B and B > A | Output | Output |
---|---|---|---|---|---|---|
Output | Output | Port 4 | Port 8 | |||
0.2825 | 0.07 | 0.25 | Logic 1 | Logic 0 | ON | OFF |
0.07 | 0.63 | 0.25 | Logic 0 | Logic 1 | OFF | ON |
0.002 | 0.62 | 0.25 | Logic 0 | Logic 1 | OFF | ON |
1.75 | 0.05 | 0.25 | Logic 1 | Logic 0 | ON | OFF |
Assigning Input Signals to Ports for the Sum Output (∑) | Assigning Input Signals to Ports for the Output Carry (Cout) | ||||
---|---|---|---|---|---|
Port 1 | Port 2 | Port 3 | Port 5 | Port 6 | Port 7 |
Ci | B | A | Ci | B | A |
Ci | B | A | A | B | Ci |
Ci | B | A | Ci | A | B |
Ci | B | A | Ci | B | A |
A | B | Ci | Ci | B | A |
Ci | B | A | Ci | B | A |
Ci | B | A | Ci | B | A |
Ci | B | A | Ci | B | A |
Input | Input | Input | Input 1 | Input 2 | Input 3 | Input 1 | Input 2 | Input 3 |
---|---|---|---|---|---|---|---|---|
State 1 | State 2 | State 3 | (Phase) | Port 2 | (Phase) | (Phase) | (Phase) | (Phase) |
(Phase) | ||||||||
Logic 0 | Logic 0 | Logic 0 | OFF (0) | OFF (0) | OFF (0) | OFF (0) | OFF (0) | OFF (0) |
Logic 0 | Logic 0 | Logic 1 | OFF (0) | OFF (0) | ON (0) | OFF (0) | OFF (0) | ON (0) |
Logic 0 | Logic 1 | Logic 0 | OFF (0) | ON (0) | OFF (0) | OFF (0) | ON (0) | OFF (0) |
Logic 0 | Logic 1 | Logic 1 | OFF (0) | ON (180) | ON (45) | OFF (0) | ON (0) | ON (0) |
Logic 1 | Logic 0 | Logic 0 | ON (0) | OFF (0) | OFF (0) | ON (0) | OFF (0) | OFF (0) |
Logic 1 | Logic 0 | Logic 1 | ON (180) | OFF (0) | ON (45) | ON (0) | OFF (0) | ON (0) |
Logic 1 | Logic 1 | Logic 0 | ON (180) | ON (45) | OFF (0) | ON (0) | ON (0) | OFF (0) |
Logic 1 | Logic 1 | Logic 1 | ON (0) | ON (0) | ON (0) | ON (0) | ON (0) | ON (0) |
T (Port 4) | T (Port 8) | Tthresh | Sum | Output | Output | Output |
---|---|---|---|---|---|---|
Output | Carry | Port 4 | Port 8 | |||
0 | 0 | 0.25 | Logic 0 | Logic 0 | OFF | OFF |
0.2825 | 0.07 | 0.25 | Logic 1 | Logic 0 | ON | OFF |
0.274 | 0.07 | 0.25 | Logic 1 | Logic 0 | ON | OFF |
0.02 | 1.12 | 0.25 | Logic 0 | Logic 1 | OFF | ON |
0.2897 | 0.07 | 0.25 | Logic 1 | Logic 0 | ON | OFF |
0.07 | 0.62 | 0.25 | Logic 0 | Logic 1 | OFF | ON |
0.07 | 0.63 | 0.25 | Logic 0 | Logic 1 | OFF | ON |
1.74 | 1.74 | 0.25 | Logic 1 | Logic 1 | ON | ON |
Criteria/Article) | This Article | Ref. [10] | Ref. [11] | Ref. [12] | Ref. [13] | Ref. [14] |
---|---|---|---|---|---|---|
Software Program Used | FEM-2D | FEM-2D | Finite Difference Time FEM-2D Domain | Finite Difference Time FEM-2D Domain | Finite Difference Time FEM-2D Domain | FEM-2D |
Proposed Structure | Nano-Rings Insulator-Metal-Insulator (IMI) Plasmonic Nano-Waveguides | Plasmonic Metal Slot Waveguides | Linear Interference Effects in Dielectric Crossed Waveguide Structure | Ring Resonator Based Metal–Insulator–Metal (MIM) Plasmonic Waveguides | Mach–Zehnder Interferometer (MZI) Using a Plasmonic MIM Waveguides | Nonlinear Plasmonic Nanoca vities |
Number of Proposed Combinational Logic Functions | 4 Combinational Logic Functions | 1 Combinational Logic Functions | 1 Combinational Logic Functions | 2 Combinational Logic Functions | 1 Combinational Logic Functions | 1 Combinational Logic Functions |
Proposed Combinational Logic Functions | Half-Adder, Half-Subtractor, Comparator One-Bit, and Full-Adder | Half-Adder | Half-Adder | Half-Adder and Half-Subtractor | Compar ator One-Bit | Half-Adder Full-Adder |
Size | 850 nm × 400 nm | Not Available | 10 µm × 28 µm | More than 1260 nm × 1260 nm | 17 µm × 3 µm | Less than 15 µm × 15 µm |
Operating Wave-Length (s) | 1550 nm | 530 nm | 800 nm | 630 nm, 901 nm, 1770 nm, and 1856 nm | 1550 nm | 750 nm and 770 nm |
Dielectric Material Used | Teflon | SiO2 | Organically Modified Silica (ORMOSIL) | Air | Non-Linear Kerr Material | Air |
Nobel Material Used | Silver | Gold | Gold | Silver | Silver | Gold |
Model of Description the Relative Permittivity of the Metal | Johnson and Christy Data | Not Available | Not Available | Drude–Lorentz Model | Drude–Lorentz Model | Not Available |
Performance Measured | Transmission | Output Optical Power | Intensity | Transmission | Intensity | Transmission and Contrast Ratio |
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Abdulnabi, S.H.; Abbas, M.N. Design an All-Optical Combinational Logic Circuits Based on Nano-Ring Insulator-Metal-Insulator Plasmonic Waveguides. Photonics 2019, 6, 30. https://doi.org/10.3390/photonics6010030
Abdulnabi SH, Abbas MN. Design an All-Optical Combinational Logic Circuits Based on Nano-Ring Insulator-Metal-Insulator Plasmonic Waveguides. Photonics. 2019; 6(1):30. https://doi.org/10.3390/photonics6010030
Chicago/Turabian StyleAbdulnabi, Saif Hasan, and Mohammed Nadhim Abbas. 2019. "Design an All-Optical Combinational Logic Circuits Based on Nano-Ring Insulator-Metal-Insulator Plasmonic Waveguides" Photonics 6, no. 1: 30. https://doi.org/10.3390/photonics6010030