This letter proposed a coarse-fine two stages time-based analog-to-digital converter (TBADC). The coarse 4-bit TBADC is pipelined with the fine 5-bit TBADC for high conversion rate. There is one bit redundancy to tolerate the gain and offset mismatch between the coarse and fine stages. The residue is transferred by splitting the capacitor array in a fully passive way, which is non-attenuated and consumes less power. The dynamic VTC in this design has a high linearity over a wide input range. The proposed ADC is designed in a 65-nm CMOS technology. It consumed 3.1mW at 1GHz and had a Walden figure of merit of 15.9fJ/conversion step.