This brief presents a 0.18-μm BCD low-dropout regulator (LDO) designed for low-power Internet of Things (IoT) devices that achieves fast transient responses with a nA-level quiescent current (IQ) and operates without external capacitors. The power supply voltage can be reduced to 0.9 V, consuming only 284 nA of quiescent current. The design incorporates an adaptive bias and a class-AB OTA with dual Gm stages, achieving low IQ. Its second stage forms a feedforward path, utilizing only a 2 pF compensation capacitor. The combination of this feedforward path and an FVF buffer with body bias modulation enables zero-point load tracking compensation technology, ensuring loop stability under light loads in this capacitor-less LDO. Moreover, reducing the size of the pass transistor MP minimizes the overall area of the LDO to just 0.005 mm². An FVF buffer integrated with a comparator-based transient enhancement circuit improves the LDO’s transient response. Post-simulation results demonstrate a load regulation of 0.0974 mV/mA, and a superior transient figure-of-merit (FOM) of 1.14-fs.

In digital DC-DC converter systems, factors such as noise, line mismatches, process variations between chips, and common mode level shifts can cause the overall system output voltage to deviate from expectations. This paper proposes a code-search-based accuracy calibration technique for the delay line based ADC in digital DC-DC converter system. By adjusting the calibration module and automatically searching for the maximum output code value, this technique effectively enhances the quantization accuracy of the ADC. The overall chip is fabricated using 0.18 μm CMOS technology, and the ADC occupies an area of 750 μm × 940 μm. Experiment results demonstrate that this technique can improve the ADC’s quantization accuracy to 94.7% and reduce the overall DC-DC loop offset from 2.8% to 0.2%, significantly enhancing the accuracy of the DC-DC output.

In modern system on a chip (SoC), input/output (I/O) devices typically utilize direct memory access (DMA) and access virtual memory in the regular way. Additionally, operating system (OS) tends to allocate physical I/O memory contiguously. To reduce latency overhead due to page-table walks, hardware often employs translation lookaside buffer (TLB) prefetch techniques. Recently, TLB coalescing schemes that merge contiguous pages into a TLB entry have been reported. However, the conventional TLB prefetchers operate in the page level and do not effectively leverage the advantages of contiguous allocation. In this paper, we present the TLB prefetcher that exploits both contiguous allocation and TLB coalescing for I/O devices. The presented prefetcher operates in the block level, exploits contiguity in memory, requires no history tracking schemes, and can reduce page-table walks compared to the conventional scheme. Our experiments indicate that the presented scheme can improve both TLB and I/O device performance.

In this study, we present a method for filling molten solder into through-glass via (TGV) substrates using a pulse width modulated (PWM) vacuum suction system. The TGV substrates were fabricated using micro-electro-mechanical systems (MEMS) techniques, incorporating anodic bonding and glass reflow processes. The vacuum suction system comprises a vacuum chuck, pressure sensor, pulse control circuit, and solenoid valve. The solenoid valve modulates the vacuum level of the chuck by opening and closing. The switching frequency was set to 1 Hz with a 20% duty cycle. TGVs were fabricated in the glass substrates with diameters of 150 μm and thicknesses of 350 μm. The vacuum filling yield was approximately 30% at 40 kPa and exceeded 98% at 80 kPa vacuum level. X-ray imaging confirmed void-free filling results. The individual via resistance of the tin-filled TGVs was measured at 69.8±38.5 mΩ using the four-probe method.

To improve the performance of the boost circuit, a fuzzy inference systems (FIS) design method based on adaptive neural networks (ANN) system identification is proposed for the boost circuit. Using ANN for system identification based on training data to generate initial first-order Takagi-Sugeno (T-S) FIS. Adjust the FIS parameters by comparing them with the testing and checking data, and iterate until the error is within an acceptable range to form the final FIS. The steady-state and dynamic capabilities of the boost circuit under FIS control have been verified through simulation and experiments to be superior to traditional proportion integral differential (PID) control. The experimental results show that when the input voltage jumps from 28 V to 22 V, the boost speed of the boost circuit based on FIS control is improved by 21.5% compared to PID.

Analog computing-in-memory (ACIM) is one promising solution to address the memory bottleneck existing in traditional computing architectures. However, inefficient analog-to-digital converters (ADC) will inhibit the performance improvement of this system. The primary contribution is in two aspects. First, we present a weight-flip-store coding technology that reduces the ADC resolution by one bit while maintaining the inference accuracy. Second, we propose a readout mechanism that can adaptively choose to skip high three-bit quantization cycles depending on input sparsity, further reducing ADC power. The experimental results show that the ADC power can be reduced by 28.5%-44.4%.

In this paper, we propose a novel MIMO-enabled integrated sensing and backscatter communication (MIMO-ISABC) system to serve multiple users, and focus on the transmit beamforming design for the system. Under the total transmit power constraint, we aim to design sensing and communication beams that meet both tag detection and communication requirements. First, we use minimum mean square error (MMSE) beamforming to design the beamforming vectors, followed by convex optimization to allocate power between sensing and communication. Then, we investigate a joint beamforming optimization problem to minimize the total transmit power while meeting the tag detection and communication requirements. To solve this, we transform the non-convex constraints into convex second-order cone constraints. The experimental results demonstrate the validity and performance of the proposed scheme and associated algorithms. The proposed MIMO-ISABC system offers great potential for applications in IoT scenarios.

Junction temperature calibration of power devices is important for estimating the junction temperature. In this paper, a pulse-current calibration method is proposed as a means of improving the efficiency of temperature calibration, utilizing the on-state voltage of SiC MOSFET as a calibration parameter. Firstly, the junction temperature calibration platform is constructed and a suitable parameter acquisition system is implemented. Subsequently, the corresponding calibration strategy and experimental flow are proposed, and the calculation of bus capacitance and inductance is given. Ultimately, the self-heating of the SiC MOSFET during the calibration is evaluated quantificationally. The results demonstrate that the self-heating effects associated with the proposed calibration method are negligible, thereby confirming the feasibility of the proposed strategy. Furthermore, the method is capable of acquiring a substantial amount of data in a single experimental test, which markedly enhances the efficiency of the calibration process.

A low-power, fast-response transmitter based on frequency-shift keying (FSK) is presented and used in the Sub-GHz band. This transmitter uses the closed-loop modulation structure of a phase-locked loop (PLL) and maintains the constant loop bandwidth of a PLL to ensure a consistent data rate at each frequency point of Sub-GHz. A fast and accurate VCO frequency sub-band selection technology is proposed to reduce the selection time of the optimal variable capacitor array control bits of VCO, thus improving the response speed of PLL and transmitter. This transmitter is implemented in the SMIC 0.18 μm CMOS process. The measured results showed that the selection time of the optimal VCO frequency sub-band is only 3.04 us, and the Error Vector Magnitude (EVM) of the whole transmitter is 4.17% at 115 kHz data rate, meeting the wireless transmission requirements of the nodes of Internet of things.

This paper proposes a high-speed transceiver-based method for implementing a digital-to-time converter (DTC). A real-time decoding technique is introduced to inject time information into high-speed pattern data. The stability of the high-speed clock ensures the high precision of the synthesized timing signal without the need for calibration. The reconfigurability of the clock resources provides the DTC with variable resolution and enhanced flexibility for various applications. Based on this approach, a multifunctional DTC is designed to offer both timing sequence and random timing signal functionalities, catering to a wide range of application scenarios. The timing sequence function generates a continuously variable timing signal stream, while the random timing signal function produces random signals with uniformly distributed time intervals. Experimental results, using a Xilinx Kintex-7 FPGA, validate the effectiveness of the proposed methodology. The system achieves a resolution of 100 ps, a dynamic range from 1 ns to 40 μs, a DNL of -0.02/0.02 LSB, an INL of -0.04/0.03 LSB across the entire range. This approach can be readily adapted to various high-precision timing signal applications.

This paper presents a highly integrated, relatively high data rate wake-up receiver (WuRX) designed and implemented in 65 nm CMOS technology. The receiver operates at 2.4 GHz band and exhibits robustness against power supply variations, and achieves a data rate of 20 kbps. It employs a sub-threshold enhanced differential structure for the envelope detector to enhance noise performance and a bias-free baseband amplifier to improve the sensitivity. Operating at a nominal voltage of 0.5 V, the WuRX consumes just 98 nW and achieves a sensitivity of -62.8 dBm.

This article presents a novel low dropout regulator with high PSR and reliable stability. In order to achieve high PSR, this design use PSR enhance circuit to filter the voltage ripple from reference at low frequency, and achieving -82 dB PSR at 1 KHz with the load of 20 mA. Besides, owing to the dynamic RC compensation network, this design can reconfigure the compensation resistor and capacitor, and achieve good stability at full load up to 250 mA. Finally, this design was implemented with the 0.5-μm CMOS technology, and the total quiescent current of the proposed LDO is only 12 μA.

This paper presents a SerDes receiver for medium-reach interconnection in a 28-nm CMOS process. It employs a CTLE and an adaptive quarter-rate loop-unrolling 5-tap DFE utilizing an SS-LMS algorithm to enable adaptive adjustment of tap coefficients under different channels. The proposed DFE contains CML-based summer with CMFB technology and two-stage dynamic comparator with an offset calibration loop. Simulation results show that this receiver can operate at 25 Gb/s data rate with a power efficiency of 5.99 pJ/bit, Its BER is less than 1E-12 and eye-wide-opening is 0.67 UI under 20.6-dB channel loss at 12.5 GHz Nyquist frequency.