[go: up one dir, main page]
Skip to main content
SpringerLink
Log in

Options for Denormal Representation in Logarithmic Arithmetic

  • Published:
Journal of Signal Processing Systems Aims and scope Submit manuscript

Abstract

Economical hardware often uses a FiXed-point Number System (FXNS), whose constant absolute precision is acceptable for many signal-processing algorithms. The almost-constant relative precision of the more expensive Floating-Point (FP) number system simplifies design, for example, by eliminating worries about FXNS overflow because the range of FP is much larger than FXNS for the same wordsize; however, primitive FP introduces another problem: underflow. The Signed Logarithmic Number System (SLNS) offers similar range and precision as FP with much better performance (in terms of power, speed and area) for multiplication, division, powers and roots. This paper proposes three variations of a new number system, respectively called the Denormal LNS (DLNS), Denormal Mitchell LNS (DMLNS) and Denormal Offset Mitchell LNS (DOMLNS), which are all hybrids of the properties of FXNS and SLNS. The inspiration for D(OM)LNS comes from the denormal (aka subnormal) numbers found in IEEE-754 (that provide better, gradual underflow) and the μ-law often used for speech encoding; the novel DLNS circuit here allows arithmetic to be performed directly on such encoded data. The proposed approach allows customizing the range in which gradual underflow occurs. Our first DLNS implementation leverages existing SLNS basic blocks. Synthesis shows the novel circuit primarily consists of traditional SLNS addition and subtraction tables, with additional datapaths that allow the novel arithmetic unit to act on conventional SLNS as well as DLNS and mixed data, for a worst-case area overhead of 26 %. Unlike SLNS, this DLNS implementation is still costly for general (non-constant) multiplication, division and roots. To overcome this difficulty, this paper proposes the other variations called Denormal Mitchell LNS (DMLNS) and Denormal Offset Mitchell LNS (DOMLNS), in which the well-known Mitchell’s method makes the cost of general multiplication, division and roots closer to that of SLNS. Taylor-series computations suggest subnormal values in DMLNS and DOMLNS also behave similarly to those in the IEEE-754 FP standard. Synthesis shows that DMLNS and DOMLNS respectively have average area overheads of 25 % and 17 % compared to an equivalent SLNS 5-operation unit.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10

Similar content being viewed by others

References

  1. Arnold, M.G., Bailey, T.A., Cowles, J.R., Cupal, J.J. (1990). Redundant logarithmic arithmetic. IEEE Transactions on Computers, 39, 1077–1086.

    Article  Google Scholar 

  2. Arnold, M.G., Bailey, T.A., Cowles, J.R., Winkel, M.D. (1992). Applying features of IEEE 754 to sign/logarithm arithmetic. IEEE Transactions on Computers, 41, 1040–1050.

    Article  Google Scholar 

  3. Arnold, M., & Walter, C. (2001). Unrestricted faithful rounding is good enough for some LNS applications. In 15th international symposium on computer arithmetic (pp. 237–245). Vail.

  4. Arnold, M., & Collange, C. (2009). A dual-purpose real/complex logarithmic number system ALU. In 19th international symposium computer arithmetic (pp. 15–24). Portland.

  5. Arnold, M., et al. (2011). Towards a quaternion complex logarithm number system. In 20th international symposium on computer arithmetic (pp. 33–42). Tuebingen.

  6. Chen, C., & Yang, C.H. (2000). Pipelined computation of very large word-length LNS addition/subtraction with polynomial hardware cost. IEEE Transactions on Computers, 49(7), 716–726.

    Article  Google Scholar 

  7. Chester, E.I., & Coleman, J.N. (2002). Matrix engine for signal processing applications using the logarithmic number system. In Proceedings of the IEEE international conference on application-specific systems, architectures and processors (pp. 315–324). San Jose.

  8. Coleman, J. N., Chester, E. I., Softley, C. I., Kadlac, J. (2000). Arithmetic on the European logarithmic microprocessor. IEEE Transactions on Computers, 49(7), 702–715.

    Article  Google Scholar 

  9. Coleman, J.N., Softley, C.I., Kadlec, J., Matousek, R., Tichy, M., Pohl, Z., Hermanek, A., Benschop, N.F. (2008). The European logarithmic microprocessor. IEEE Transactions on Computers, 57(4), 532–546.

    Article  MathSciNet  Google Scholar 

  10. de Dinechin, F. (2011). The arithmetic operators you will never see in a microprocessor. In 20th international symposium on computer arithmetic (pp. 189–190). Tuebingen.

  11. de Dinechin, F., Joldes, M., Pasca, B. (2010). Automatic generation of polynomial-based hardware architectures for function evaluation. In Application-specific systems, architectures and processors. IEEE.

  12. Edgar, A. D., & Lee, S. C. (1979). FOCUS microcomputer number system. Communications of the ACM, 22, 166–167.

    Article  Google Scholar 

  13. Fu, H., Mencer, O., Luk, W. (2010). FPGA designs with optimized logarithmic arithmetic. IEEE Transactions on Computers, 59(7), 1000–1006.

    Article  MathSciNet  Google Scholar 

  14. Gauss, K.F. (1900). Werke (vol. 8, pp. 121–128).

  15. IEEE Standard for Binary Floating-Point Arithmetic (1985). ANSI/IEEE Std 754-1985. IEEE.

  16. IEEE Standard for Floating-Point Arithmetic (2008). ANSI/IEEE Std 754-2008. IEEE.

  17. Ismail, R.C., & Coleman, J.N. (2011). ROM-less LNS. In 20th international symposium on computer arithmetic (pp. 43–51). Tuebingen.

  18. Kidd, S.J. (1983). Implementation of the sign-logarithm arithmetic FFT. Royal signals and radar establishment memorandum 3644. Malvern.

  19. Kingsbury, N.G., & Rayner, P.J.W. (1971). Digital filtering using logarithmic arithmetic. Electronics Letters, 7(2), 56–58.

    Article  Google Scholar 

  20. Kahrs, M., & Branderburg, K., (Eds.) (1998). Applications of digital signal processing to audio and acoustics (p. 224). Norwell: Kluwer Academic Publishing.

  21. Lewis, D.M. (1995). 114 MFLOPS logarithmic number system arithmetic unit for DSP applications. In International solid-state circuits conference (pp. 1547–1553). San Francisco.

  22. Dimitrov, V.S., Eskritt, J., Imbert, L., Jullien, G.A., Miller, W.C. (2001). The use of the multi-dimensional logarithmic number system in DSP applications. In 15th international symposium on computer arithmetic (pp. 247–254). Vail.

  23. Kouretas, I., Basetas, Ch., Paliouras, V. (2011). Low-power logarithmic number system addition and subtraction and their impact on digital filters. In IEEE transactions on computers. IEEE Computer Society Digital Library. doi:10.1109/TC.2012.111

  24. Makino, J., & Taiji, M. (1998). Scientific simulations with special-purpose computers—the GRAPE systems. Chichester: Wiley.

  25. Paliouras, V., & Stouraitis, T. (2001). Low power properties of the logarithmic number system. In Proceedings of the 15th IEEE symposium on computer arithmetic (pp. 229–236). Vail.

  26. Swartzlander, E.E., Chandra, D., Nagle, T., Starks, S.A. (1983). Sign/logarithm arithmetic for FFT implementation. IEEE Transactions on Computers, C-32, 526–534.

    Article  Google Scholar 

  27. Swartzlander, E.E., & Alexopoulos, A.G. (1975). The sign/logarithm number system. IEEE Transactions on Computers, C-24, 1238–1242.

    Article  MathSciNet  Google Scholar 

  28. Young, S., et al. (2001). The HTK book (for HTK Version 3.1). England: Cambridge University Engineering Department, http://htk.eng.cam.ac.uk.

  29. www.xlnsresearch.com has an extensive bibliography of LNS-related articles.

  30. Pulse Code Modulation (PCM) of Voice Frequencies (1988). International Telecomunications Union. http://www.itu.int/rec/T-REC-G.711/en.

  31. Mitchell, J.N. (1962). Computer multiplication and division using binary logarithms. IEEE Transactions on Electronic Computer, EC-11, 512–517.

    Article  MathSciNet  Google Scholar 

  32. Abed, K.H., & Siferd, R.E. (2003). CMOS VLSI implementation of a low-power logarithmic converter. IEEE Transactions on Computers, 52(11), 1421–1433.

    Article  Google Scholar 

  33. Abed, K.H., & Siferd, R.E. (2003). VLSI implementation of a low-power antilogarithmic converter. IEEE Transactions on Computers, 52(9), 1221–1228.

    Article  Google Scholar 

  34. Bhairannawar, S., et al. (2012). FPGA based recursive error-free mitchell log multiplier for image filters. In IEEE international conference on computational intelligence and computing research (ICCIC) (pp. 1–5). Coimbatore. doi:10.1109/ICCIC.2012.6510248.

  35. Mahalingam, V., & Ranganathan, N. (2006). Improving accuracy in Mitchell’s logarithmic multiplication using operand decomposition. IEEE Transactions on Computers, 55(12), 1523–1535.

    Article  Google Scholar 

  36. McLaren, D.J. (2003). Improved Mitchell-based logarithmic multiplier for low-power DSP applications. In IEEE international system on chip (SOC) conference (pp. 53–56).

  37. Sullivan, M., & Swartzlander, E.E. (2013). Truncated logarithmic approximation. In 21th symposium on computer arithmetic. Austin.

  38. Shetty, D.R., & Patil, S. (2013). Improving accuracy in Mitchell’s logarithmic multiplication using iterative multiplier for image processing application. International Journal of Soft Computing and Engineering (IJSCE), 3(3), 187–191. ISSN: 2231-2307.

    Google Scholar 

  39. Layer, C., Pfleiderer, H.J., Heer, C. (2004). A scalable compact architecture for the computation of integer binary logarithms through linear approximation. In 2004 international symposium on circuits and systems (ISCAS) (vol. 2, pp. 421–424). Vancouver.

  40. Marsono, M.N., El-Kharashi, M.W., Gebali, F. (2006). Binary LNS-based Nave Bayes hardware classifier for spam control. In IEEE international symposium on circuits and systems (ISCAS) (pp. 3674–3677). Kos.

  41. Page, A., & Mosemnin, T. (2013). An efficient and reconfigurable FPGA and ASIC Implementation of a Spectral Doppler Ultrasound Imaging System. In 21th symposium on computer arithmetic. Austin.

  42. Maenner, R. (1987). A fast integer binary logarithm of large arguments. IEEE Microwave, 7(6), 41–45.

    Article  Google Scholar 

  43. Arnold, M., Bailey, T., Cowles, J., Cupal, J. (2002). Error analysis of the Kmetz/Maenner algorithm. Journal of VLSI Signal Processing, 33, 37–53.

    Article  Google Scholar 

  44. Arnold, M. G. (2004). LPVIP: a low-power ROM-Less ALU for low-precision LNS. In 14th international workshop on power and timing modeling, optimization and simulation (pp. 675–684). LNCS 3254, Santorini.

  45. Arnold, M.G., & Vouzis, P. (2007). A serial logarithmic number system ALU. In EuroMicro digital system design DSD (pp. 151–156). Lubeck.

  46. Arnold, M. G. (2013). Improved DNA-sticker arithmetic: tube-encoded-carry, logarithmic number system and Monte-Carlo methods. Natural Computing, 12(2), 235–246.

    Article  MathSciNet  Google Scholar 

  47. Arnold, M.G., & Collange, C. (2013). The Denormal logarithmic number system. In 24th international conference on application specific systems, architectures and processors (ASAP). Washington.

  48. Li, S.-Y.R. (1985). Fast constant division routines. IEEE Transactions on Computers, C-34, 866–869.

    Article  Google Scholar 

  49. Jacobsohn, D.H. (1973). A combinatoric division algorithm for fixed-integer division. IEEE Transactions on Computers, C-22, 608–610.

    Article  Google Scholar 

Download references

Acknowledgments

We wish to thank the reviewers from their insightful comments and suggestions.

Author information

Authors and Affiliations

  1. XLNS Research, PO Box 605, Laramie, WY, 82070, USA

    Mark G. Arnold

  2. INRIA, Centre de recherche Rennes - Bretagne Atlantique, Rennes, France

    Caroline Collange

Authors
  1. Mark G. Arnold
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Caroline Collange
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Caroline Collange.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Arnold, M.G., Collange, C. Options for Denormal Representation in Logarithmic Arithmetic. J Sign Process Syst 77, 207–220 (2014). https://doi.org/10.1007/s11265-014-0874-3

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-014-0874-3

Keywords

Search

Navigation