This webpage is an attempt to be an exhaustive list of Logarithmic Number System references, but naturally it is incomplete. If you have additions or corrections, PLEASE email to the first author of “A Real/Complex Logarithmic Number System ALU” below using the email address (all lower case no space or punctuation): first name middle initial last name at sign this website. In other words, m...d@x...com 　

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Khalid H. Abed and R. E. Siferd, ``CMOS VLSI Implementation of a Low-Power Logarithmic Converter,” IEEE Transactions on Computers, vol. 52, no. 11, pp. 1421-1433, Nov. 2003.

Khalid H. Abed and R. E. Siferd, ``VLSI Implementation of a Low-Power Antilogarithmic Converter,” IEEE Transactions on Computers, vol. 52, no. 9, pp. 1221-1228, Sept. 2003.

Khalid H. Abed and R. E. Siferd, ``CMOS VLSI Implementation of 16-bit Logarithm and Anti-logarithm Converters,” Proceedings of the 43rd IEEE Midwest Circuits and Systems, 2000, vol. 2, pp. 776-779, Aug. 2000.

Nacer Abouchi and Romuald Gallorini, ``Exponential and Logarithmic Functions Using Standard CMOS 0.8 um Technology,” Analog Integrated Circuits and Signal Processing,” vol. 27, no. 1, pp. 73-83, Apr. 2001.

Nacer Abouchi, Romuald Gallorini and C. Ruby, ``Exponential and Logarithmic Functions Using Standard CMOS 0.8 um Technology,” Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems (ICECS'99), vol. 1, pp. 189-192, Pafos, Cyprus, 5-8 Sept. 1999.

F. Albu, Jiri Kadlec, Nick Coleman and Anthony Fagan, ``The Gauss-Seidel Fast Affine Projection Algorithm,” Proceedings of the IEEE Workshop on Signal Processing Systems (SIPS '02), pp. 109-114, San Diego, 16-18 Oct. 2002.

F. Albu, C. Paleologu and S. Ciochina, ``Analysis of LNS Implementation of the QRD-LSL Algorithms,” Proceedings of the International Symposium on Communications Systems, Networks and Digital Signal Processing (CSNDSP'02), pp. 364-367, Staffordshire, UK, 15-17 July 2002.

F. Albu, J. Kadlec, A. Fagan, A. Hermanek and N. Coleman, ``Analysis of the LNS Implementation of the Fast Affine Projection Algorithms,” Proceedings of ISSC 2002, pp. 251-255, Cork, Ireland, June 2002.

F. Albu, Jiri Kadlec, Nick Coleman and Anthony Fagan, ``Pipelined Implementations of the A Priori Error-Feedback LSL Algorithm Using Logarithmic Number System,” Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing, 2002, vol. 3, pp. 2681-2684, Orlando, Florida, 13-17 May 2002.

Felix Albu, Jiri Kadlec and J. Nick Coleman Implementation of Error-Feedback RLS Lattice on Virtex Using Logarithmic Arithmetic, Research Report, Academy of Sciences of the Czech Republic, Institute of Information Theory and Automation, Prague, 2001.

Felix Albu, Jiri Kadlec and J. N. Coleman, ``Implementation of Error-Feedback RLS Lattice on Virtex Using Logarithmic Arithmetic,” 5th WSES Multiconference on Circuits, Systems, Communications & Computers (CSCC 2001), pp. 517-521, Rethymno, Greece, 2001.

Felix Albu, Jiri Kadlec, R. Matousek, A. Hermanek and J. Nick Coleman, A Comparison of FPGA Implementations of the a Priori Error-Feedback LSL Algorithm Using Logarithmic Arithmetic, Research Report, Academy of Sciences of the Czech Republic, Institute of Information Theory and Automation, Prague, 2001.

T. Harish Anand, D. Vaithiyanathan and R Seshasayanan, ``Optimized Architecture for Floating Point Computation Unit," International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT), Tiruvannamalai, pp. 1-5, 7-9 Jan. 2013. doi:10.1109/ICEVENT.2013.6496587

M. H. Andoyer, ``Tables Fondamentales pour les Logarithmes d'Addition et de Soustraction,” Bulletin Astronomique, vol. 2, pp. 5-32, 1922.

V.M. Amerbaev, A.I. Kornilov and A.L. Stempkovsky, ``Residue Logarithmic Number System – A New Possibilities for Residue Processors and Converters Designing," Proceedings of Problems of Perspective Micro- and Nanoelectronic Systems Development, ed. A. Stempkovsky, Moscow, IPPM RA, pp. 368-373, 2010. http://www.mes-conference.ru/data/year2010/papers/m10-273-59962.pdf

Mark G. Arnold, and Sylvain Collange, ``The Denormal Logarithmic Number System", 24th International Conference on Application Specific Systems, Architectures and Processors, Washington, DC, June 2013.

M.G. Arnold, ``Improved DNA-sticker Arithmetic: Tube-encoded-carry, Logarithmic Number System and Monte-Carlo methods," Natural Computing, Vol. 12, no. 2, pp. 235-246, 2013.

M.G. Arnold, ``An Improved DNA-Sticker Addition Algorithm and Its Application to Logarithmic Arithmetic," 17th International Conference on DNA Computing, Pasadena, LNCS, vol. 6937, pp. 34-48, Sept. 2011.

M.G. Arnold, V. Paliouras, I. Kouretas, ``A Residue Logarithmic Number System ALU Using Interpolation and Cotransformation," 22th International Conference on Application-specific Systems, Architectures and Processors, Santa Monica, pp. 255-258, Sept. 2011. doi:10.1109/ASAP.2011.6043281

M.G. Arnold, J.R. Cowles, V. Paliouras, I. Kouretas, ``Towards a Quaternion Complex Logarithmic Number System," International Symposium on Computer Arithmetic, Tübingen, Germany, pp. 33-42, July 2011. doi: 10.1109/ARITH.2011.14

Mark G. Arnold and Sylvain Collange, ``A Real/Complex Logarithmic Number System ALU,” IEEE Transactions on Computers, vol. 60, no. 2, pp. 202-213, February, 2011. doi: 10.1109/TC.2010.154

M. Arnold, S. Collange, D. Defour, ``Implementing LNS Using Filtering Units of GPUs," Proceedings of the IEEE International Conference on Acoustics, Speech, Signal Processing, pp. 1542-1545, Dallas, Texas, 14 March 2010.

Mark G. Arnold and Sylvain Collange, ``A Dual-Purpose Real/Complex Logarithmic Number System ALU,” IEEE Symposium on Computer Arithmetic, pp. 15-24, Portland, Oregon, 8 June 2009.

Mark G. Arnold and Panos Vouzis, ``A Serial Logarithmic Number System ALU,” EuroMicro Digital System Design DSD, pp. 151-156, Lubeck, Germany, 29 Aug. 2007.

Mark G. Arnold, ``A RISC Processor with Redundant LNS Instructions,” EuroMicro Digital System Design DSD, pp. 475-482, Dubrovnik, Croatia,1 Sept. 2006.

Mark G. Arnold, ``Approximating Trigonometric Functions with the Laws of Sines and Cosines Using the Logarithmic Number System,” EuroMicro Symposium on Digital Systems Design, pp. 48-53, Porto, Portugal, Aug. 30 - Sept. 3 2005.

Mark G. Arnold and P. Leong, ``Logarithmic Arithmetic for N-body Simulation,” Proceedings of the Work- in-Progress Session of 31st EuroMicro Conference, Porto, Portugal, pp. 24-25, Porto, Portugal, Sept. 3 2005.

M. Arnold and J. Ruan, ``Bipartite Implementation of the Residue Logarithmic Number System,” International Symposium on Optical Science and Technology SPIE Annual Meeting, pp. 196-205. San Diego, Aug. 2005.

Mark G. Arnold, ``The Residue Logarithmic Number System: Theory and Implementation,” 17th International Symposium on Computer Arithmetic, pp. 196-205, Cape Cod, MA, 27-29 June 2005.

Mark G. Arnold, ``LPVIP: A Low-power ROM-Less ALU for Low-Precision LNS,” 14th International Workshop on Power and Timing Modeling, Optimization and Simulation, LNCS 3254, pp. 675-684, Santorini, Greece, 15-17 Sept. 2004.

Mark G. Arnold, ``Redundant Logarithmic Arithmetic for MPEG Decoding,” International Symposium on Optical Science SPIE Annual Meeting 2004, Denver, Colorado, 2-6 Aug. 2004.

M. G. Arnold, “Geometric-Mean Interpolation for Logarithmic Number Systems,” Proceedings of the 2004 International Symposium on Circuits and Systems (ISCAS'04), vol. 2, pp. 433-436, Vancouver, Canada, 23-26 May 2004.

M. Arnold, T. Bailey, J. Cowles and C. Walter, ``Fast Fourier Transform Using the Complex Logarithmic Number System,” Journal of VLSI Signal Processing, vol. 33, no. 3, pp. 325-335, 2003.

M. G. Arnold, J. Garcia and M. Schulte, ``The Interval Logarithmic Number System,” 16th IEEE International Symposium on Computer Arithmetic(ARITH-16'03), pp. 253-261, Santiago de Compostela, Spain, 15-18 June 2003.

Mark Arnold, ``Asymmetric and Compressed Logarithmic Number Systems for a Multimedia Coprocessor,” Proceedings of the 37th Asilomar Conference on Signals, Systems and Computers, pp. 1426-1430, Pacific Grove CA, 9-12 Nov. 2003.

Mark Arnold, ``A VLIW Architecture for Logarithmic Arithmetic,” Proceedings of the EuroMicro Digital System Design (DSD'03), pp. 294-302, Antalya, Turkey, 1-6 Sept. 2003.

Mark G. Arnold, ``Iterative Methods for Logarithmic Subtraction,” The IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP'03), pp. 315-325, Hague, Netherlands, 24-26 June 2003.

Mark G. Arnold, ``Avoiding Oddification to Simplify MPEG-1 Decoding with LNS,” IEEE International Workshop on Multimedia Signal Processing, St. Thomas, Virgin Islands, Dec. 2002.

M. Arnold, T. Bailey, J. Cowles and J. Cupal, ``Error Analysis of the Kmetz/Maenner Algorithm,” Journal of VLSI Signal Processing, vol. 33, pp. 37-53, Oct. 2002.

Mark G. Arnold, ``LNS for Low-Power MPEG Decoding,” Proceedings of SPIE Advanced Signal Processing, Architectures and Implementations XII, vol. 4791, pp. 369-380, Seattle, Washington, 9-1 July 2002.

Mark G. Arnold, ``Reduced Power Consumption for MPEG Decoding with LNS,” The IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP'02), pp. 65-75, San Jose, CA, 17-19 July 2002.

Mark G. Arnold, Logarithmic Number Systems for MPEG and Multimedia Applications, PhD thesis, University of Manchester Institute of Science and Technology, 2002.

Mark G. Arnold, ``An Improved Cotransformation for Logarithmic Subtraction,” Proceedings of the International Symposium on Circuits and Systems (ISCAS'02), pp. 752-755, Scottsdale, Arizona, 26-29 May 2002.

Mark G. Arnold, ``Slide Rules for the 21st Century: Logarithmic Arithmetic as a High-speed, Low-cost, Low-power Alternative to Fixed Point Arithmetic,” Second Online Symposium for Electronics Engineers, 2001.

Mark G. Arnold, Thomas A. Bailey, John R. Cowles and Colin Walter, ``Analysis of Complex LNS FFTs,” Francky Catthoor and Marc Moonen, editors, Proceedings of Signal Processing Systems SIPS 2001: Design and Implementation, pp. 58-69, Antwerp, Belgium, 26-28 Sept. 2001. IEEE Press.

Mark G. Arnold, ``Design of a Faithful LNS Interpolator,” Proceedings of the EuroMicro Digital System Design (DSD'01), pp. 336-345, Warsaw, Poland, 4-6 Sept. 2001.

Mark G. Arnold and Mark D. Winkel, ``A Single-Multiplier Quadratic Interpolator for LNS Arithmetic,” Proceedings of the 2001 International Conference on Computer Design (ICCD'01), pp. 178-183, Austin, Texas, 23-26 Sept. 2001.

M. Arnold and M. Winkel, ``Reconfiguring an FPGA-based RISC for LNS Arithmetic,” Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, Proceedings of SPIE, vol. 4525, pp. 88-98, Denver, 21-22 Aug. 2001.

Mark G. Arnold and C. Walter, ``Unrestricted Faithful Rounding is Good Enough for Some LNS Applications,” Proceedings of the 15th International Symposium on Computer Arithmetic, pp. 237-246, Vail, Colorado, 11-13 June 2001.

Mark G. Arnold, ``A Pipelined LNS ALU,” IEEE Workshop on VLSI, Orlando, Florida, 19-20 April 2001.

Mark Arnold, Colin Walter and Freddy Engineer, ``Verilog Transcendental Functions for Numerical Testbenches,” Proceedings of the 10th International HDL Conference, Santa Clara, California, 1 March 2001.

M. G. Arnold, F. N. Engineer and M. D. Winkel, ``AWE: The ARM Workalike Experiment,” WESTCON, San Jose, California, 21 Oct. 1999. www.cs.uwyo.edu/~marnold/awe.html.

M. G. Arnold, T. A. Bailey, J. R. Cowles and M. D. Winkel, ``Arithmetic Co-transformations in the Real and Complex Logarithmic Number Systems,” IEEE Transactions on Computers, vol. 47, no. 7, pp. 777-786, July 1998.

M. G. Arnold, T. A. Bailey, J. R. Cowles and M. D. Winkel, ``Arithmetic Co-transformations in the Real and Complex Logarithmic Number Systems,” Proceedings of the 13th IEEE Symposium on Computer Arithmetic(ARITH-13), pp. 190-197, Asilomar, California, 6-9 July 1997.

M. G. Arnold, T. A. Bailey, J. J. Cupal and M. D. Winkel, ``On the Cost Effectiveness of Logarithmic Arithmetic for Back-Propagation Training on SIMD Processors,” Proceedings of the 1997 International Conference on Neural Networks, vol. 2, pp. 933-936, Houston, Texas, 9-12 June 1997.

M. G. Arnold, Method and Apparatus for Fast Logarithmic Addition and Subtraction, United States Patent 5,337,266, 9 Aug. 1994.

M. G. Arnold, T. A. Bailey, J. R. Cowles and M. D. Winkel, ``Applying Features of IEEE 754 to Sign/Logarithm Arithmetic,” IEEE Transactions on Computers, vol. 41, no. 8, pp. 1040-1050, Aug. 1992.

M. Arnold, T. Bailey and J. Cowles, ``Comments on `An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System’,” IEEE Transactions on Computers, vol. 41, no. 6, pp. 786-788, June 1992.

M. Arnold, T. Bailey, J. Cowles and J. Cupal, ``Initializing RAM-based Logarithmic Processors,” Journal of VLSI Signal Processing, vol. 4, no. 2-3, pp. 243-252, May 1992.

M. Arnold, T. Bailey, J. Cowles and J. Cupal, ``Implementing Back-Propagation Neural Nets with Logarithmic Arithmetic,” Proceedings of the International AMSE Conference Neural Networks, vol. 1, pp. 75-86, San Diego, California, May 1991.

M. G. Arnold, T. A. Bailey, J. R. Cowles and J. J. Cupal, ``Redundant Logarithmic Arithmetic,” IEEE Transactions on Computers, vol. 39, no. 8, pp. 1077-1086, Aug. 1990.

M. Arnold, T. Bailey, J. Cowles and J. Cupal. ``Redundant Logarithmic Number Systems,” Proceedings of the 9th Symposium on Computer Arithmetic, pp. 144-157, Santa Monica, CA, 6-8 Sept. 1989.

M. G. Arnold, T. A. Bailey and J. R. Cowles, ``Improved Accuracy for Logarithmic Addition in DSP Applications,” Proceedings of the IEEE International Conference on Acoustics, Speech, Signal Processing, vol. 3, pp. 1714-1717, 1988.

Mark G. Arnold, Extending the Precision of the Sign Logarithm Number System, Master's thesis, University of Wyoming, Laramie, 1982.

Mahzad Azarmehr and Majid Ahmadi, ``Low-Power Finite Impulse Response (FIR) Filter Design Using Two-Dimensional Logarithmic Number System (2DLNS) Representations," Circuits, Systems, and Signal Processing, vol. 31, no. 6, pp 2075-2091, Dec. 2012. doi: 10.1007/s00034-012-9417-y

Mahzad Azarmehr, Arithmetic with the Two-Dimensional Logarithmic Number System (2DLNS), PhD Disertation, University of Windsor, 2011.

Mahzad Azarmehr and Roberto Muscedere, ``A RISC Architecture for 2DLNS-based Signal Processing," International Journal of High Performance Systems Architecture, Vol. 3, No. 2-3, pp. 149-156, 2011. doi: 10.1504/IJHPSA.2011.040467

M. Azarmehr, M. Ahmadi, M. and G. A. Jullien, ``A Two-Dimensional Logarithmic Number System (2DLNS)-Based Finite Impulse Response (FIR) Filter Design," IEEE 9th International New Circuits and Systems Conference (NEWCAS), Bordeaux, pp. 37-40, 26-29 June 2011. doi: 10.1109/NEWCAS.2011.5981213

M. Azarmehr, M. Ahmadi, M. and G. A. Jullien and R. Muscedere, ``High-speed and Low-power Reconfigurable Architectures of 2-digit Two-Dimensional Logarithmic Number System-based Recursive Multipliers," IET Circuits, Devices & Systems, vol. 4 , no. 5, pp. 374-381, Sept. 2010. doi: 10.1049/iet-cds.2009.0329

M. Azarmehr, M. Ahmadi, and G. A. Jullien, ``Recursive Architectures for 2DLNS Multiplication," IEEE International Symposium on Circuits and Systems, pp. 3869-3872, 2010.

Mahzad Azarmehr and Roberto Muscedere, ``A Simple Central Processing Unit with Multi-Dimensional Logarithmic Number System Extensions," Application Specific Systems, Architectures and Processors, pp. 342-345, Montreal, Quebec, 9 July 2007. pp. 342-345. doi: 10.1109/ASAP.2007.4430003

M. Azarmehr, ``A Multi-Dimensional Logarithmic Number System Based CPU”, http://www.vlsi.uwindsor.ca/presentations/2006/A Multi-Dimensional Logarithmic Number Dimensional Logarithmic Number_Mahzad.pdf

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Zdenka Babic, Aleksej Avramovic and Patricio Bulic, ``An Iterative Logarithmic Multiplier," Electrotechnical Review, Ljubljana, Slovenija, vol. 77, no. 1., pp. 25–30, 2010.

Z. Babic, A. Avramovic, P. Bulic, ``An iterative logarithmic multiplier," Microprocessors & Microsystems, vol. 35, pp. 23-33, 2011.

P. W. Baker, ``More Efficient Radix-2 Algorithms for Some Elementary Functions,” IEEE Transactions on Computers, 24, pp. 1049-1054, Nov. 1975.

E.S. Balaka, V.M. Amerbaev, A.V. Konstantinov and D.V. Telpukhov, ``Methods of Scalar Products Speed Enhancement in Residue Logarithmic Number System Basis," Proceedings of Problems of Perspective Micro- and Nanoelectronic Systems Development, 2010, ed. A. Stempkovsky, Moscow, IPPM RAS, pp. 378-381, 2010. http://www.mes-conference.ru/data/year2010/papers/m10-270-53062.pdf

G.B. Balaji, K. Balaji, H. Sundararaman, A. Naveen and K. R. Santha, ``Memory Reduction Techniques for Logarithmic Number System," International Conference on Signal Processing, Communications and Networking, Chennai, pp. 410 - 413, 22-24 Feb. 2007.

R. Bannister, D. Gregg, S. Wilson and A. Nisbet, ``FPGA Implementation of an Image Segmentation Algorithm Using Logarithmic Arithmetic," 48th Midwest Symposium on Circuits and Systems, vol. 1, pp. 810 - 813, 7-10 Aug. 2005.

E. H. Bareiss and A. A. Grau, Basics of the CRD Computer, ERDA Report COO-2280-25, Northwestern University, Aug. 1977.

J. L. Barlow, ``On Roundoff Error Distributions in Floating Point and Logarithmetic Arithmetic,” Computing, vol. 34, no. 4, pp. 325-347, Oct. 1985.

J. L. Barlow, ``Probabilistic Error Analysis of Gaussian Elimination in Floating Point and Logarithmic Arithmetic,” Computing, vol. 34, no. 4, pp. 349-364, Oct. 1985.

J. L. Barlow, Probabilistic Error Analysis of Floating Point and CRD Arithmetics, PhD thesis, Northwestern University, Evanston, Illinois,, 1981.

J. L. Barlow. Probabilistic Error Analysis of Computer Arithmetics, Master's thesis, Northwestern University, Evanston, Illinois, 1979.

Ch. Basetas, I. Kouretas and V. Paliouras, ``Low-Power Digital Filtering Based on the Logarithmic Number System," Lecture Notes in Computer Science Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation, pp. 546-555, 2007.

A. Bechtolsheim and T. Gross, ``The Implementation of Addition in Logarithmic Arithmetic,” R. Lyon A. Bell, L. Conway and M. Newell, editors, Proceedings of the MPC79 Multi-University Chip Set Project, Xerox PARC Report, 15 March 1980.

A. Bechtolsheim and T. Gross, ``The Implementation of Addition in Logarithmic Arithmetic,” unpublished paper, Computer Systems Lab, Stanford University, 1980.

N. Belanger, Y. Savaria, ``On the Design of a Double Precision Logarithmic Number System Arithmetic Unit," IEEE North-East Workshop on Circuits and Systems, Gatineau, Que., pp. 241 - 244, 18-21 June 2006.

R. W. Bemer, ``Subroutine Method for Calculating Logarithms,” Communications of the ACM, vol. 1, no. 5, pp. 5-7, 1958.

F. Berens, A. Worm, H. Michel and N.When, ``Implementation Aspects of Turbo-Decoders for Future Radio Applications,” Proceedings of the IEEE Vehicular Technology Conference (VTC) Fall 1999, vol. 5, pp. 2601-2605, Amsterdam, Sept. 1999.

Satish Bhairannawar et al., ``FPGA based Recursive Error-Free Mitchell Log Multiplier for Image Filters," IEEE International Conference on Computational Intelligence & Computing Research (ICCIC), Coimbatore, India, pp. 1-5, 18-20 Dec. 2012. doi: 10.1109/ICCIC.2012.6510248

L. G. Bleris, P. D. Vouzis, J. G. Garcia, M. G. Arnold and M. V. Kothare, ``Pathways for Optimization-Based Drug Delivery,” Control Engineering Practice Journal, Special Issue for ADCHEM Symposium, vol. 15, no. 10, pp 1280-1291, Oct. 2007.

L. Bleris, J. G. Garcia and M. G. Arnold and M. V. Kothare, ``Model Predictive Hydrodynamic Regulation of Microflows,” Journal of Micromechanics and Microengineering, vol. 16, pp. 1792-1799, July 2006.

L. G. Bleris, P. D. Vouzis, M. G. Arnold and M. V. Kothare, ``A Co-Processor FPGA Platform for the Implementation of Real-Time Model Predictive Control,” American Control Conference (ACC-06), Minneapolis, Minnesota, 14 June 2006.

L. G. Bleris, P. D. Vouzis, M. G. Arnold and M. V. Kothare, ``Pathways for Optimization-Based Drug Delivery Systems and Devices,” International Symposium on Advanced Control of Chemical Processes (ADCHEM-06), Gramado, Brazil, 2 April 2006.

L. Bleris, J. G. Garcia and M. G. Arnold and M. V. Kothare, ``Towards Embedded Model Predictive Control for System-on-a-Chip Applications,” Journal of Process Control, vol. 16, no. 3, pp. 255-264, March 2006.

Leonidas Bleris, Mayuresh V. Kothare, Jesus Garcia and Mark G. Arnold, ``Embedded Model Predictive Control for System-On-a-Chip Applications,” Proceedings of the 7th International Symposium on Dynamics and Control of Process Systems, Boston, July 2004.

A. Boni and A. Zorat, ``FPGA Implementation of Support Vector Machines with Pseudo-Logarithmic Number Representation," International Joint Conference on Neural Networks (IJCNN ), pp. 618-624, 2006. doi: 10.1109/IJCNN.2006.246740

G. E. Bottomley, R. Ramesh, P. W. Dent and S. Chennakeshu, Despreading of Direct Sequence Spread Spectrum Communications Signals, U.S. Patent 6,005,887, 21 Dec. 1999. Assigned to Ericsson.

E. Boutillon, W. J. Gross and G. Gulak, ``VLSI Architectures for the MAP Algorithm,” IEEE Transactions on Communications, vol. 51, no. 2, pp. 175-185, Feb. 2003.

I. F. Numerisches Rechnen. pp. 1018-1020.

T. Brabec, ``Speculatively Redundant Continued Logarithmic Representation,” IEEE Transactions on Computers, vol. 59, no. 11, pp. 1441-1454, Nov. 2010.

R. Brent, ``On the Precision Attainable with Various Floating-Point Number Systems,” IEEE Transactions on Computers, C-vol. 22, no. 6, pp. 601-607, June 1973.

A. Brokalakis and V. Paliouras, ``Using the Arithmetic Representation Properties of Data to Reduce the Area and Power Consumption of FFT Circuits for Wireless OFDM Systems," IEEE Workshop on Signal Processing Systems (SiPS), Beirut, pp. 7-12, 4-7 Oct. 2011. doi: 10.1109/SiPS.2011.6088941

T. A. Brubaker and J. C. Becker. ``Multiplication Using Logarithms Implemented with Read-Only Memory,” IEEE Transactions on Computers, vol. 24, no. 8, pp. 761-765, Aug. 1975.

T. A. Brubaker, ``Multiplication Using Logarithmic Arithmetic,” Electronic Letters, vol.7, pp. 56-58, pp. 215-217, 1971.

P. Bulic, Z. Babic, and A. Avramovic, ``A simple pipelined logarithmic multiplier," IEEE International Conference on Computer Design (ICCD), Amsterdam, pp. 235-240, 3-6 Oct. 2010. doi:10.1109/ICCD.2010.5647767

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O. Callanan, A. Nisbet, E. Ozer, J. Sexton and D. Gregg, ``FPGA Implementation of a Lattice Quantum Chromodynamics Algorithm Using Logarithmic Arithmetic," 19th IEEE International Parallel and Distributed Processing Symposium, pp. 146b-146b, 4-8 April 2005. doi: 10.1109/IPDPS.2005.228

Owen Callanan, David Gregg, Andy Nisbet and Mike Peardon, ``High performance scientific computing using FPGAS with IEEE floating point and logarithmic arithmetic for lattice QCD," International Conference on Field Programmable Logic and Applications, Madrid, pp. 29-34, Aug. 2006.

D. Cantor, G. Estrin and R. Turn. ``Logarithm and Exponential Function Evaluation in a Variable Structure Digital Computer,” IRE Transactons on Computers, pp. 155-164, April 1962.

S. Carrillo, H. Carrillo, and F. Viveros, ``Design and Implementation of an Arithmetic Processor Unit Based on the Logarithmic Number System," IEEE Latin America Transactions (Revista IEEE America Latina), vol.8, no.6, pp. 605-617, Dec. 2010. doi: 10.1109/TLA.2010.5688085

Anindita Chakraborty and Amitabha Sinha, ``Conversion of binary to single-term triple base numbers for DSP applications," ACM SIGARCH Computer Architecture News, Vol. 39, no. 5, pp. 5-11, Dec. 2011. doi: 10.1145/2093339.2093342

Roger Chamberlain, Eric Hemmeter, Robert Morley and Jason White, ``Modeling the Power Consumption of Audio Signal Processing Computations Using Customized Numerical Representations,” Proceedings of the 36th Annual Simulation Symposium, pp. 249-255, Orlando, Florida, 30 March - 2 April 2003. http://www.ccrc.wustl.edu/~roger/papers/chmw03.pdf.

Roger Chamberlain, Yen Hsiang Chew, Varuna DeAlwis, John Lockwood Eric Hemmeter, Robert Morley, Ed Richter, Jason White and Huakai Zhang, ``Power Consumption of Customized Numerical Representations for Audio Signal Processing,” 6th High Performance Embedded Computing Workshop, Sept. 2002. www.ccrc.wustl.edu/~roger/papers/ccdhlmrwz02b.pdf.

Roger Chamberlain, Yen Hsiang Chew, Varuna DeAlwis, Eric Hemmeter, John Lockwood, Robert Morley, Ed Richter, Jason White and Huakai Zhang, ``Novel Numerical Representations for Low-Power Audio Signal Processing,” International Hearing Aid Research Conference, Aug. 2002. www.ccrc.wustl.edu/~roger/papers/ccdhlmrwz02.pdf.

D. V. Chandra, ``Error Analysis of FIR Filters Implemented Using Logarithmic Arithmetic,” IEEE Circuits and Systems: Analog and Digital Signal Processing, vol. 45, no. 6, pp. 744-747, June 1998.

D. V. Chandra, ``Accumulation of Coefficient Roundoff Error in Fast Fourier Transforms Implemented with Logarithmic Number System,” IEEE Transactions on Acoustics, Speech and Signal Processing, vol. 35, no. 11, pp. 1633-1636, Nov. 1987.

D. V. Chandra, V. P. Nelson and S. A. Stark, ``Distributed Logarithmic FFT Processor,” Proceedings of Southeastcon '81, pp. 210-214, 5-8 April 1981.

J.H. Chang , J.T. Yen and K.K. Shung, ``A Novel Envelope Detector for High-frame Rate, High-Frequency Ultrasound Imaging," IIEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control , vol. 54, no. 9, pp. 1792-1801, 2007. doi: 10.1109/TUFFC.2007.463 http://www.ncbi.nlm.nih.gov/pmc/articles/PMC2717899/

Jin Chang, Lei Sun, Yen, J.T. and K.K. Shung, ``Low-cost, High-speed Back-end Processing System for High-frequency Ultrasound B-mode Imaging," IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control, Vol. 56, No. 7, pp. 1490-1497, July 2009. doi: 10.1109/TUFFC.2009.1205

C. Chen, ``Error Analysis of LNS Addition/subtraction with Direct-computation Implementation," IET Computers & Digital Techniques, vol. 3, no. 4, pp. 329-337, July 2009. doi:10.1049/iet-cdt.2008.0098

C. Chen, L.W. Liu and J.W. Jou, ``Software Implementation of LNS Arithmetic in an ARM Embedded System," IEEE 13th International Symposium on Consumer Electronics, Kyoto, pp. 1012 - 1014, 25-28 May 2009.

C. Chen and P. Chow, ``Design of a Versatile and Cost-effective Hybrid Floating-point/LNS Arithmetic Processor," Proceedings of the 17th ACM Great Lakes Symposium on VLSI, Stresa-Lago Maggiore, Italy, pp. 540-545, 11-13 March 2007.

C. Chen and C. H. Yang, ``Pipelined Computation of Very Large Word-Length LNS Addition / Subtraction with Polynomial Hardware Cost,” IEEE Transactions on Computers, vol. 47, no. 9, pp. 716-726, July 2000.

C. Chen and C. H. Yang, ``Pipelined Computation of LNS Addition/Subtraction with Very Small Lookup Tables,” Proceedings of the International Conference on Computer Design, pp. 292-297, 5-7 Oct. 1998.

C. C. Chen and Y. Y. Chen, ``Error Analysis of DCT Algorithms in Floating Point and Logarithmic Number Systems,” 9th VLSI Design / CAD Symposium, pp. 313-316, Nan-Tow, Taiwan, 1998.

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Freedom CPU (a collaborative effort to develop a microprocessor placed in the public domain.)

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Interactive Machines Inc., IMI-500 graphics workstation. This firm built graphics workstations during the 1980's. One model used in 1985, the IMI-500, apparently used LNS to speed up graphics.

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P. Sucha, Z. Pohl and Z. Hanzalek, ``Scheduling of Iterative Algorithms on FPGA with Pipelined Arithmetic Unit," 10th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2004), Toronto, pp. 404 - 412, 25-28 May 2004.

Michael Sullivan and Earl Swartzlander, ``Truncated Logarithmic Approximation," IEEE Symposium on Computer Arithmetic, Austin, TX, April 2013.

T.J. Sullivan, ``Estimating the Power Consumption of Custom CMOS Digital Signal Processing Integrated Circuits for Both the Uniform and Logarithmic Number Systems,” Report ESSRL-93-7, Electronic Systems and Signals Research Laboratory, Department of Electrical Engineering, Washington University, Saint Louis, Missouri, 1993. More recent publications are at: http://www.ee.siue.edu/~mentor/research/VLSI.html, http://www.ee.siue.edu/~mentor/research/ANA.html, http://www.ee.siue.edu/~mentor/research/DHA.html.

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Earl E. Swartzlander and Barry K. Gilbert, ``Arithmetic for Ultra-High-Speed Tomography,” IEEE Transactions on Computers, vol. 29, no. 5, pp. 341-353, 1980.

E. Swartzlander, ``Comment on 'The Focus Number System',” IEEE Transactions on Computers, vol. 28, no. 9, pp. 693, Sept. 1979.

E. Swartzlander and B. K. Gilbert, ``High Speed Computerized Tomography,” Proceedings of the Society of Photo-Optical Instrumentation Engineers, vol. 119, pp. 299-306, 1977.

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F. J. Taylor, R. Gill, J. Joseph and J. Radke, ``A 20 Bit Logarithmic Number System Processor,” IEEE Transactions on Computers, 37, pp. 190-199, 1988.

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F. J. Taylor, ``Reconfigurable Binary/RNS/LNS Architecture for DSP,” Proceedings of the 1987 International Conference on Acoustics, Speech and Signal Processing, pp. 503-506, April 6-9 1987.

F. J. Taylor, ``Hybrid Floating-Point Logarithmic Number System Processor,” IEEE Transactions on Circuits and Systems, vol. 32, no. 1, pp. 92-95, Jan. 1985.

F. J. Taylor, ``A Logarithmic Arithmetic Unit for Signal Processing,” Proceedings ICASSP, pp. 44.10.1-44.10.4, 1984.

F. J. Taylor, ``An Extended Precision Logarithmic Number System,” IEEE Transactions on Acoustics, Speech and Signal Processing, vol. 31, no. 1, pp. 232-234, Feb. 1983.

D.H.Y. Teng, Hu Song and Dinh Anh, ``A Technology-Independent Logarithmic Converter IP Block," Canadian Conference on Electrical and Computer Engineering, Vancouver, BC, pp. 1376-1379, 22-26 April 2007

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Russell Tessier and Wayne Burleson, ``Reconfigurable Computing for Digital Signal Processing: A Survey,” Journal of VLSI Signal Processing, vol. 28, no. 1-2, pp. 7-27, 2001.

Milan Tichy, Jan Schier and David Gregg, ``GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systems," ACM Transactions on Embedded Computing Systems (TECS), Vol. 9, No. 3, February 2010. doi: 10.1145/1698772.1698787

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Y. Uchiyama and H. Suzuki, ``Electronic Musical Instrument Forming Tones by Wave Computation,” United States Patent 4,616,546, Oct. 14 1986. Assigned to Yamaha. This patent uses logarithmic arithmetic to implement FM synthesis for Yamaha's musical synthesizers. For more information refer to Applications of Digital Signal Processing to Audio and Acoustics (M. Kahrs and K. Branderburg editors, Kluwer Academic Publishers, Norwell, MA, 1998) or see http://www.musemagic.com/papers/DSPworld.html.

PRO-DASP VIVA 2002, 2002. Project at the Univ. of Hamburg is developing a power efficient macro-module library for audio signal processing. Some of the designs apparently use LNS. For more information see http://ima-www.informatik.uni-hamburg.de/Papers/2002/prodasp_viva_02.html. http://getwww.uni-paderborn.de/viva/kolloquien/kolloquien/vortraege-02/voss_mertsching.pdf http://subs.emis.de/LNI/Proceedings/Proceedings67/GI-Proceedings.67-112.pdf

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O. Vainio, ``Biased Logarithmic Arithmetic in FIR Filters," Electronics Letters, vol. 41, no.10, 580-581, 12 May 2005.

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N. Venkateswaran, Vasanth Ramesan, R. Subramanian and S. Praveen, ``A Mixed Number System Based Low Power High Performance Arithmetic Processor for DSP Applications,” Proceedings of the International Signal Processing Conference (ISPC'03), vol. 2, pp. 421-424, Dallas, Texas, 1-3 April 2003.

V. L. Volkov and P. V. Pakshin, ``Logarithmic Number System in Control Algorithms and Information Processing,” Soviet Journal of Computer and Systems Sciences, vol. 30, no. 1, pp. 132-138, Jan.-Feb. 1992.

P. Vouzis, Collange, S., M. G. Arnold and M. V. Kothare, ``Improving Model Predictive Control Arithmetic Robustness by Monte-Carlo Simulations," IET Control Theory & Applications, Vol. 6, no. 8, pp. 1064-1070, May 2012. doi: 10.1049/iet-cta.2010.0736

P. Vouzis, L. G. Bleris, J. Garcia, M. G. Arnold and M. V. Kothare, “Embedded Real-Time Model Predictive Control on-a-Chip,” U. S. Patent 7,844,352, filed Oct. 20, 2006, issued Nov, 20, 2010.

P. D. Vouzis, S. Collange and M. G. Arnold, ``A Novel Cotransformation for LNS Subtraction,” Journal of VLSI Signal Processing, vol. 59, no. 1, pp. 29-40, Jan. 2010.

P. D. Vouzis, L. G. Bleris, M. G. Arnold and M. V. Kothare, ``A System-on-a-Chip Implementation for Embedded Real-Time Model Predictive Control,” IEEE Transactions on Control Systems Technology, vol. 17, no. 5, pp. 1006-1017, Sept. 2009.

P. D. Vouzis, S. Collange and M. G. Arnold, ``Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS Subtraction,” Euromicro Conference on Digital System Design, pp. 85-93, Lubeck, Germany, 29 Aug. 2007.

P. D. Vouzis, S. Collange, M. G. Arnold and M. Kothare, ``Monte-Carlo Logarithmic Number System for Model Predictive Control,” Proceedings of the 17th International Conference on Field Programmable Logic and Applications, pp. 453-458, Amsterdam, Netherlands, 27 Aug. 2007.

P. D. Vouzis, S. Collange and M. G. Arnold, ``LNS Subtraction Using Novel Cotransformation and/or Interpolation,” Application Specific Systems, Architectures and Processors, pp. 107-114, Montreal, Quebec, 9 July 2007.

P. D. Vouzis, M. G. Arnold, L. G. Bleris, M. V. Kothare and Yongho Cha, ``A Coprocessor Accelerator for Model Predictive Control,” Proceedings of the Fifth Workshop on Optimization for DSP and Embedded Systems, pp. 76-77, San Jose, CA, 11 March 2007.

P. D. Vouzis, M. G. Arnold, L. G. Bleris and M. V. Kothare, ``Model Predictive Control for Embedded Applications,” AIChE Annual Meeting, Nov. 2006.

P. D. Vouzis, M. G. Arnold and M. V. Kothare, ``Evaluating Robustness of Model Predictive Control Using Monte-Carlo Simulations,” AIChE Annual Meeting, Nov. 2006.

P. D. Vouzis, L. G. Bleris, M. G. Arnold and M. V. Kothare, ``A Custom-Made Algorithm-Specific Processor for Model Predictive Control,” International Symposium of Industrial Electronics (ISIE06), Montreal, Quebec, pp. 228-233, 9 July 2006.

Panagiotis Vouzis and Mark Arnold, ``A Parallel Search Algorithm for CLNS Addition Optimization,” IEEE International Symposium on Circuits and Systems, pp. 2417-2420, Kos, Greece, 21-24 May 2006.

P. Vouzis, L. G. Bleris, M. V. Kothare and M. G. Arnold, ``Towards a Co-design Implementation of a System for Model Predictive Control,” AIChE Annual Meeting, Cincinnati, Ohio, Nov. 2005.

P. Vouzis, M. G. Arnold and V. Paliouras, ``Using CLNS for FFTs in OFDM Demodulation of UWB Receivers,” The IEEE International Symposium on Circuits and Systems 2005, vol. 4, pp. 3954-3957, Kobe, Japan, 23-26 May 2005.

Panayiotis Vouzis and Vassilios Paliouras, ``Optimal Logarithmic Representation in Terms of SNR Behavior,” 14th International Workshop on Power and Timing Modeling, Optimization and Simulation LNCS 3254, number 3254, pp. 760-769, Santorini, Greece, 15-17 Sept. 2004.

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Y. Wan and C. L. Wey, ``Efficient Algorithms for Binary Logarithmic Conversion and Addition,” IEEE Proceedings, Computers and Digital Techniques, vol. 146, pp. 168-176, May 1999.

Y. Wan and C. L. Wey, ``Efficient Algorithms for Binary Logarithmic Conversion and Addition,” Proceedings IEEE International Symposium on Circuits and Systems, vol. V, pp. 233-236, Monterey, CA,, May 1998.

A. Wang, ``Annals of the History of Computing,” 1993. This summary of Dr. An Wang's career gives an overview of the LOCI (LOgarithmic Computing Instrument) desktop calculator that Wang Labs introduced in 1964.

A. Wang, Calculating Apparatus, United States Patent 3,402,285, Sep. 17 1968. Assigned to Wang Labs.

S. T. Wang, S. C. Ma, J. M. Richey and S. Pan, ``Method and System for Digital Beam Forming,” United States Patent 5,917,447, June 29 1999. Assigned to Motorola.

Yan Wang, Hing Mo Lam, Chi Ying Tsui, R. S. Cheng and Wai Ho Mow, ``Low Complexity OFDM Receiver Using Log-FFT for Coded OFDM System,” Proceedings of the 2004 International Symposium on Circuits and Systems (ISCAS'02), vol. 3, pp. 445-448, Scottsdale, Arizona, 26-29 May 2002.

Yan Wang, C.Y. Tsui, R.S. Cheng and Wai Ho Mow, ``Performance Study of OFDM Receiver Using FFT Based on Log Number System,” IEEE Semiannual Vehicular Technology Conference (VTC-02), vol. 55, pp. 1257-1259, Birmingham, Alabama, USA, 6-9 May 2002.

M. Wazlowski, A. Smith, R. Citro and H. Silverman, ``Performing Log-Scale Addition on a Distributed Memory MIMD Multicomputer with Reconfigurable Computing Capabilities,” Proceedings of the 1995 International Conference on Parallel Processing, vol. 3, pp. III-211 - III-214, Urbana-Champain, Illinois, USA, Aug. 14-18 1995.

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Jianhua Xiao and Mengyao Zhu, ``A hardware implement of phong shader in 3D graphics," IET International Communication Conference on Wireless Mobile and Computing (CCWMC 2011), Shanghai, pp. 503-507, 14-16 Nov. 2011. doi: 10.1049/cp.2011.0939

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Gurtac Yemiscioglu and Peter Lee, ``16-Bit Clocked Adiabatic Logic (CAL) Leading One Detector for a Logarithmic Signal Processor," 8th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Aachen, Germany, pp. 1-4, 12-15 June 2012.

S. Young, G. Evermann, D. Kershaw, G. Moore, J. Odell, D. Ollason, V. Valtchev and P. Woodland, The HTK Book (for HTK Version 3.1), Cambridge University Engineering Department, Dec. 2001. Available: http, //htk.eng.cam.ac.uk/. Note: HTK is a popular toolkit (based on a 15-bit LNS) that is widely used by researchers to implement Hidden Markov Models for speech recognition.

M. I. Youssef, ``A New Stable Second-Order Section for Recursive Digital Filters Realized with Logarithmic Arithmetic,” 11th Mediterranean Electrotechnical Conference, MELCON 2002, pp. 308-314, May 7-9 2002.

E. C. Yowell and G. Blanch, ``A Guide to Tables on Punched Cards,” MTAC, v. 5, pp. 185-202, 1951.

L. K. Yu and D. M. Lewis, ``A 30-bit Integrated Logarithmic Number System Processor,” IEEE Journal of Solid-State Circuits, vol. 26, no. 10, pp. 1433-1440, Oct. 1991.

L. Yu, Design and Implementation of a 30-bit Logarithmic Number Processor, Master's thesis, Univ. of Toronto, Jan. 1990.

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P. Zdenek, T. Milan and K. Jiri, ``Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA,”, EURASIP Journal on Advances in Signal Processing, vol. 2008, Article ID 394201, 11 pages, 2008. doi:10.1155/2008/394201

G. Zelniker and F. J. Taylor, ``A Reduced Complexity Finite Field ALU,” IEEE Transactions on Circuits and Systems, vol. 38, no. 12, pp. 1571-1573, Dec. 1991.

Wenjing Zhang, G. A. Jullien and V. S. Dimitrov, ``A Programmable Base 2D-LNS MAC with Self-generated Lookup Tables,” Proceedings of the 2004 International Symposium on Circuits and Systems (ISCAS'04), vol. 2, pp. 789-792, Vancouver, Canada, 23-26 May 2004.

M. Zhang and V. Asari, ``A fully pipelined multiplierless architecture for 2d convolution with quadrant symmetric kernels," IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Dec. 2006, pp. 1559-1562.

Yang Zhen-Xi, Zhang Li, and Nie Zhi-Liang, ``Optimized Algorithm for Hardware Implementation Based on SVM Probability Modeling," Computer Engineering, 2011. http://en.cnki.com.cn/Article_en/CJFDTOTAL-JSJC201123076.htm