Abstract
We explore the use of subfield arithmetic for efficient implementations of Galois Field arithmetic especially in the context of the Rijndael block cipher. Our technique involves mapping field elements to a composite field representation. We describe how to select a representation which minimizes the computation cost of the relevant arithmetic, taking into account the cost of the mapping as well. Our method results in a very compact and fast gate circuit for Rijndael encryption.
In conjunction with bit-slicing techniques applied to newly proposed parallelizable modes of operation, our circuit leads to a high-performance software implementation for Rijndael encryption which offers significant speedup compared to previously reported implementations.
As of April 2001, the author can be reached at Amazon.com, 605 5th Ave South, Seattle, WA 98104, U.S.A.
Chapter PDF
Similar content being viewed by others
Keywords
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
References
Kazumaro Aoki and Helger Lipmaa, ”Fast Implementations of AES candidates”. In Proc.Third AES Candidate Conference, April 13–14, 2000. http://csrc.nist.gov/encryption/aes/round2/conf3/aes3papers.html
Eli Biham, “A Fast New DES Implementation in Software”. In Proc. Fast Software Encryption 4,1997. http://www.cs.technion.ac.il/~biham/publications.html
Joan Daemen and Vincent Rijmen, “AES Proposal: Rijndael”. http://www.esat.kuleuven.ac.be/~rijmen/rijndael.
Keith Diefendorff, Pradeep K. Dubey, Ron Hochsprung and Hunter Scales, “AltiVec Extension to PowerPC Accelerates Media Processing”. In IEEE Micro, March-April 2000, pp85–95.
AJ Elbirt, W Yip, B Chetwynd and C Paar, “An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists”. In Proc. Third AES Candidate Conference, April 13–14, 2000. http://csrc.nist.gov/encryption/aes/round2/conf3/aes3papers.html
Tetsuya Ichikawa, Tomomi Kasuya and Mitsuru Matsui, “Hardware Evaluation of the AES Finalists”. In Proc. Third AES Candidate Conference, April 13–14, 2000. http://csrc.nist.gov/encryption/aes/round2/conf3/aes3papers.html
Charanjit S. Jutla, “Encryption Modes with Almost Free Message Integrity”. Manuscript.
Rudolf Lidl and Harald Niederreiter, Introduction to finite fields and their applications. Cambridge University Press, Cambridge, Ma., 1986.
Edoardo D. Mastrovito, VLSI Architectures for Computations in Galois Fields. PhD Thesis, Dept. of EE, Linköping University, Linköping, Sweden 1991.
Christof Paar and Pedro Soria-Rodriguez, “Fast Arithmetic Architectures for Public-Key Algorithms over Galois Fields GF((2n)n)”. In Proc. EUROCRYPT’ 97.
Chirstof Paar, Efficient VLSI Architectures for Bit-Parallel Computations in Galois Fields. PhD Thesis, Institute for Experimental Mathematics, University of Essen, Germany, 1994. http://www.ece.wpi.edu/Research/crypt/theses/paarthesispage.html.
Bruce Schneier, Applied Cryptography, John Wiley and Sons, 1996.
Bryan Weeks, Mark Bean, Tom Rozylowicz and Chris Ficke, “Hardware Performance Simulations of Round 2 Advanced Encryption Standard Algorithm”. In Proc. Third AES Candidate Conference, April 13–14, 2000. http://csrc.nist.gov/encryption/aes/round2/conf3/aes3papers.html
Richard Weiss and Nathan Binkert “A comparison of AES candidates on the Alpha 21264”. In Proc. Third AES Candidate Conference, April 13–14, 2000. http://csrc.nist.gov/encryption/aes/round2/conf3/aes3papers.html
Thomas J. Wollinger, Min Wang, Jorge Guajardo and Christof Paar, “How Well Are High-End DSPs suited for AES Algorithms?” In Proc. Third AES Candidate Conference, April 13–14, 2000. http://csrc.nist.gov/encryption/aes/round2/conf3/aes3papers.html
John Worley, Bill Worley, Tom Christian and Christopher Worley, “AES Finalists on PA-RISC and IA-64: Implementations & Performance. In Proc. Third AES Candidate Conference, April 13–14, 2000. http://csrc.nist.gov/encryption/aes/round2/conf3/aes3papers.html
“American National Standard for Information Systems — Data Encryption Algorithm — Modes of Operation”. ANSI X3.106, American National Standards Institute, 1983.
“Information processing — Modes of operation for a 64-bit block cipher algorithm”. ISO 8372, International Organisation for Standardisation, Geneva, Switzerland, 1987.
“DES modes of operation”. NBS FIPS PUB 81, National Bureau of Standards, U.S. Department of Commerce, 1980.
http://www.nist.gov/publicaffairs/releases/g00-176.htm, US Commerce Department Press Release.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2001 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Rudra, A., Dubey, P.K., Jutla, C.S., Kumar, V., Rao, J.R., Rohatgi, P. (2001). Efficient Rijndael Encryption Implementation with Composite Field Arithmetic. In: Koç, Ç.K., Naccache, D., Paar, C. (eds) Cryptographic Hardware and Embedded Systems — CHES 2001. CHES 2001. Lecture Notes in Computer Science, vol 2162. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44709-1_16
Download citation
DOI: https://doi.org/10.1007/3-540-44709-1_16
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-42521-2
Online ISBN: 978-3-540-44709-2
eBook Packages: Springer Book Archive