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2020 – today
- 2024
[c12]Bo-Han Li, Kuan-Chih Lin, Hao Zuo, Po-Cheng Pan, Hung-Ming Chen, Shyh-Jye Jou, Chien-Nan Jimmy Liu, Bo-Cheng Lai:
Efficient Analog Layout Generation for In-RRAM Computing Circuits via Area and Wire Optimization. MWSCAS 2024: 1085-1090- 2020
- [j2]Abhishek Patyal
, Po-Cheng Pan, K. A. Asha, Hung-Ming Chen, Wei-Zen Chen:
Exploring Multiple Analog Placements With Partial-Monotonic Current Paths and Symmetry Constraints Using PCP-SP. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5056-5068 (2020)
2010 – 2019
- 2019
- [c11]Po-Cheng Pan, Chien-Chia Huang, Hung-Ming Chen:
An Efficient Learning-based Approach for Performance Exploration on Analog and RF Circuit Synthesis. DAC 2019: 232 - 2018
- [c10]Abhishek Patyal, Po-Cheng Pan, K. A. Asha, Hung-Ming Chen, Hao-Yu Chi, Chien-Nan Liu:
Analog placement with current flow and symmetry constraints using PCP-SP. DAC 2018: 10:1-10:6 - [c9]Po-Cheng Pan, Hung-Wen Huang, Chien-Chia Huang, Abhishek Patyal, Hung-Ming Chen, Tsun-Yu Yang:
On Closing the Gap Between Pre-Simulation and Post-Simulation Results in Nanometer Analog Layouts. SMACD 2018: 181-184 - 2015
- [j1]Po-Cheng Pan, Ching-Yu Chin, Hung-Ming Chen, Tung-Chieh Chen, Chin-Chieh Lee, Jou-Chun Lin:
A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(9): 1373-1386 (2015) - [c8]Hui-Tang Chang, Po-Cheng Pan, Yu-Chiang Frank Wang, Ming-Syan Chen:
R2P: Recomposition and Retargeting of Photographic Images. ACM Multimedia 2015: 927-930 - 2014
- [c7]Shih-Hsin Hsu, Wei-Zen Chen, Jui-Pin Zheng, Sean S.-Y. Liu, Po-Cheng Pan, Hung-Ming Chen:
An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming. VLSI-DAT 2014: 1-4 - 2013
- [c6]Po-Cheng Pan, Hung-Ming Chen, Chien-Chih Lin:
PAGE: parallel agile genetic exploration towards utmost performance for analog circuit design. DATE 2013: 1849-1854 - [c5]Ching-Yu Chin, Po-Cheng Pan, Hung-Ming Chen, Tung-Chieh Chen, Jou-Chun Lin:
Efficient analog layout prototyping by layout reuse with routing preservation. ICCAD 2013: 40-47 - 2012
- [c4]Po-Cheng Pan, Hung-Ming Chen, Yi-Kan Cheng, Jill Liu, Wei-Yi Hu:
Configurable analog routing methodology via technology and design constraint unification. ICCAD 2012: 620-626 - 2011
- [c3]Yi-Peng Weng, Hung-Ming Chen, Tung-Chieh Chen, Po-Cheng Pan, Chien-Hung Chen, Wei-Zen Chen:
Fast analog layout prototyping for nanometer design migration. ICCAD 2011: 517-522 - [c2]Kuo-Hsuan Meng, Po-Cheng Pan, Hung-Ming Chen:
Integrated hierarchical synthesis of analog/RF circuits with accurate performance mapping. ISQED 2011: 777-784
2000 – 2009
- 2009
- [c1]Bo-Zhou Chen, Hung-Ming Chen, Li-Da Huang, Po-Cheng Pan:
A stochastic-based efficient critical area extractor on OpenAccess platform. ACM Great Lakes Symposium on VLSI 2009: 197-202
Coauthor Index
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