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ORCIDTung-Chieh Chen
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2020 – today
- 2024
[c28]Tung-Chieh Chen
:
Introduction to the Panel on EDA Challenges at Advanced Technology Nodes. ISPD 2024: 61- 2022
- [c27]Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen:
Flexible chip placement via reinforcement learning: late breaking results. DAC 2022: 1392-1393 - [i1]Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen:
Flexible Multiple-Objective Reinforcement Learning for Chip Placement. CoRR abs/2204.06407 (2022) - 2021
- [c26]Yun Chou, Jhih-Wei Hsu, Yao-Wen Chang, Tung-Chieh Chen:
VLSI Structure-aware Placement for Convolutional Neural Network Accelerator Units. DAC 2021: 1117-1122 - 2020
- [c25]Tai-Chen Chen, Pei-Yu Lee, Tung-Chieh Chen:
Automatic Floorplanning for AI SoCs. VLSI-DAT 2020: 1-2
2010 – 2019
- 2019
- [c24]Yen-Chun Liu, Tung-Chieh Chen, Yao-Wen Chang, Sy-Yen Kuo:
MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs. ASP-DAC 2019: 557-562 - 2018
- [j14]Chau-Chin Huang, Hsin-Ying Lee, Bo-Qiao Lin, Sheng-Wei Yang, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang, Tung-Chieh Chen, Ismail Bustany:
NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(3): 669-681 (2018) - [c23]Pei-Yu Lee, Iris Hui-Ru Jiang, Tung-Chieh Chen:
FastPass: Fast timing path search for generalized timing exception handling. ASP-DAC 2018: 172-177 - 2017
- [c22]Sheng-Wei Yang, Yao-Wen Chang, Tung-Chieh Chen:
Blockage-aware terminal propagation for placement wirelength minimization. ICCAD 2017: 73-80 - [c21]Szu-To Chen, Yao-Wen Chang, Tung-Chieh Chen:
An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designs. ICCAD 2017: 496-503 - [c20]Chin-Hao Chang, Yao-Wen Chang, Tung-Chieh Chen:
A novel damped-wave framework for macro placement. ICCAD 2017: 504-511 - 2015
- [j13]Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Ching-Feng Yeh, Xin Li, Tsung-Yi Ho:
A Novel Analog Physical Synthesis Methodology Integrating Existent Design Expertise. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(2): 199-212 (2015) - [j12]Po-Cheng Pan, Ching-Yu Chin, Hung-Ming Chen, Tung-Chieh Chen, Chin-Chieh Lee, Jou-Chun Lin:
A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(9): 1373-1386 (2015) - [c19]Shih-Ying Liu, Tung-Chieh Chen, Hung-Ming Chen:
An approach to anchoring and placing high performance custom digital designs. ASP-DAC 2015: 384-389 - 2014
- [j11]Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Ching-Feng Yeh, Tsung-Yi Ho, Bin-Da Liu:
Exploring Feasibilities of Symmetry Islands and Monotonic Current Paths in Slicing Trees for Analog Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(6): 879-892 (2014) - [j10]Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Sheng Chou, Tzu-Hen Lin, Tung-Chieh Chen, Yao-Wen Chang:
NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1914-1927 (2014) - 2013
- [j9]Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Tsung-Yi Ho, Yu-Chuan Chen, Shun-Ren Siao, Shu-Hung Lin:
1-D Cell Generation With Printability Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(3): 419-432 (2013) - [c18]Hsing-Chih Chang Chien, Hung-Chih Ou, Tung-Chieh Chen, Ta-Yu Kuan, Yao-Wen Chang:
Double patterning lithography-aware analog placement. DAC 2013: 4:1-4:6 - [c17]Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Tung-Chieh Chen, Yao-Wen Chang:
Routability-driven placement for hierarchical mixed-size circuit designs. DAC 2013: 151:1-151:6 - [c16]Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Tsung-Yi Ho, Yu-Chuan Chen:
Lithography-aware 1-dimensional cell generation. ECCTD 2013: 1-4 - [c15]Ching-Yu Chin, Po-Cheng Pan, Hung-Ming Chen, Tung-Chieh Chen, Jou-Chun Lin:
Efficient analog layout prototyping by layout reuse with routing preservation. ICCAD 2013: 40-47 - 2012
- [c14]Po-Hsun Wu, Mark Po-Hung Lin, Yang-Ru Chen, Bing-Shiun Chou, Tung-Chieh Chen, Tsung-Yi Ho, Bin-Da Liu:
Performance-driven analog placement considering monotonic current paths. ICCAD 2012: 613-619 - [c13]Tung-Chieh Chen, Ta-Yu Kuan, Chung-Che Hsieh, Chi-Chen Peng:
Challenges and solutions in modern analog placement. VLSI-DAT 2012: 1-4 - 2011
- [c12]Yi-Peng Weng, Hung-Ming Chen, Tung-Chieh Chen, Po-Cheng Pan, Chien-Hung Chen, Wei-Zen Chen:
Fast analog layout prototyping for nanometer design migration. ICCAD 2011: 517-522 - [c11]Tung-Chieh Chen:
Automated placement for custom digital designs. ISPD 2011: 89-90
2000 – 2009
- 2009
- [j8]Yao-Wen Chang, Zhe-Wei Jiang, Tung-Chieh Chen:
Essential Issues in Analytical Placement Algorithms. Inf. Media Technol. 4(4): 815-836 (2009) - [j7]Yao-Wen Chang, Zhe-Wei Jiang, Tung-Chieh Chen:
Essential Issues in Analytical Placement Algorithms. IPSJ Trans. Syst. LSI Des. Methodol. 2: 145-166 (2009) - 2008
- [j6]Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin:
A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2): 286-294 (2008) - [j5]Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang:
Effective Wire Models for X-Architecture Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 654-658 (2008) - [j4]Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang:
NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1228-1240 (2008) - [j3]Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Tien-Yueh Liu:
MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1621-1634 (2008) - [j2]Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang:
Metal-Density-Driven Placement for CMP Variation and Routability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2145-2155 (2008) - [c10]Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan:
An integrated nonlinear placement framework with congestion and porosity aware buffer planning. DAC 2008: 702-707 - [c9]Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang:
Metal-density driven placement for cmp variation and routability. ISPD 2008: 31-38 - [r1]Tung-Chieh Chen, Yao-Wen Chang:
Packing Floorplan Representations. Handbook of Algorithms for Physical Design Automation 2008 - 2007
- [c8]Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Denny Liu:
MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. DAC 2007: 447-452 - [c7]Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang:
X-architecture placement based on effective wire models. ISPD 2007: 87-94 - [p1]Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang:
NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs. Modern Circuit Placement 2007: 289-309 - 2006
- [j1]Tung-Chieh Chen, Yao-Wen Chang:
Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4): 637-650 (2006) - [c6]Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang:
A high-quality mixed-size analytical placer considering preplaced blocks and density constraints. ICCAD 2006: 187-192 - [c5]Zhe-Wei Jiang, Tung-Chieh Chen, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang:
NTUplace2: a hybrid placer using partitioning and analytical techniques. ISPD 2006: 215-217 - 2005
- [c4]Jen-Yi Wuu, Tung-Chieh Chen, Yao-Wen Chang:
SoC test scheduling using the B-tree based floorplanning technique. ASP-DAC 2005: 1188-1191 - [c3]Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin:
IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs. ICCAD 2005: 159-164 - [c2]Tung-Chieh Chen, Yao-Wen Chang:
Modern floorplanning based on fast simulated annealing. ISPD 2005: 104-112 - [c1]Tung-Chieh Chen, Tien-Chang Hsu, Zhe-Wei Jiang, Yao-Wen Chang:
NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs. ISPD 2005: 236-238
Coauthor Index
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