To strive for better circuit performance on analog design, layout generation heavily relies on
experienced analog designers' effort. Other than general analog constraints such as
symmetry and wire-matching are commonly embraced in many proposed works, analog
circuit performance is also sensitive to routing behavior. This paper presents a CDT-based
layout extraction to preserve routing behavior of the reference layout. Furthermore, a
generalized layout prototyping methodology is proposed based on the layout extraction to …

A computer implemented method for routing preservation is presented. The method includes
decomposing, using the computer, a geometric relationship between a first module, a
second module, and a routing path of a source layout, when the computer is invoked to route
the solution path. The method further includes disposing, using the computer, the routing
path in a solution layout in accordance with the geometric relationship. The solution layout is
not defined by a scaling of the source layout.