default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDHiroyuki Yamauchi
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2023
[c29]Zhufeng Li
, Hiroyuki Yamauchi:
Image Recognition Accuracy, Number of Parameters and Computational Complexity Using Channel Reduction by Dimensional Compression and Attention Function. ICECC 2023: 1-7- [c28]Weijie Guan, Zhufeng Li, Hiroyuki Yamauchi:
Graph Structure Exploration for Reinforcement Learning State Embedding - Train Tetris Agent with Graph Neural Network. ICECC 2023: 42-48 - 2022
- [c27]Peng Yu, Hiroyuki Yamauchi:
A Machine Learning Based Fuel Consumption Saving Method with Time and Environment Dependency Aware Management. ICECC 2022: 40-49 - 2021
- [j29]Jiazhen Xi, Hiroyuki Yamauchi:
A Layer-Wise Ensemble Technique for Binary Neural Network. Int. J. Pattern Recognit. Artif. Intell. 35(8): 2152011:1-2152011:21 (2021)
2010 – 2019
- 2019
- [j28]Cheng-Xin Xue, Wei-Cheng Zhao, Tzu-Hsien Yang, Yi-Ju Chen, Hiroyuki Yamauchi, Meng-Fan Chang:
A 28-nm 320-Kb TCAM Macro Using Split-Controlled Single-Load 14T Cell and Triple-Margin Voltage Sense Amplifier. IEEE J. Solid State Circuits 54(10): 2743-2753 (2019) - [j27]Xin Si, Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xiaoyu Sun, Rui Liu, Shimeng Yu, Hiroyuki Yamauchi, Qiang Li, Meng-Fan Chang:
A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(11): 4172-4185 (2019) - 2018
- [c26]Cheng-Xin Xue, Wei-Cheng Zhao, Tzu-Hsien Yang, Yi-Ju Chen, Hiroyuki Yamauchi, Meng-Fan Chang:
A 28mn 320Kb TCAM Macro with Sub-0.8ns Search Time and 3.5+x Improvement in Delay-Area-Energy Product using Split-Controlled Single-Load 14T Cell. A-SSCC 2018: 127-128 - [i1]Hiroyuki Yamauchi, Takashi Oguchi, Yuichi S. Hayakawa, Toshikazu Seto:
Development and operation of GIS exercise materials for undergraduate students. PeerJ Prepr. 6: e27219 (2018) - 2017
- [j26]Meng-Fan Chang, Chien-Fu Chen, Ting-Hao Chang, Chi-Chang Shuai, Yen-Yao Wang, Yi-Ju Chen, Hiroyuki Yamauchi:
A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme. IEEE J. Solid State Circuits 52(9): 2498-2514 (2017) - 2016
- [c25]Hiroyuki Yamauchi, Worawit Somha:
A filter design for blind deconvolution to decouple unknown RDF/RTN factors from complexly coupled SRAM margin variations. LASCAS 2016: 247-250 - [c24]Hiroyuki Yamauchi, Worawit Somha:
A mutual rectification-interference avoidance technique with cascade filters for both downward-direction tailed-RDF deconvolution. SBCCI 2016: 1-6 - 2015
- [c23]Meng-Fan Chang, Chien-Fu Chen, Ting-Hao Chang, Chi-Chang Shuai, Yen-Yao Wang, Hiroyuki Yamauchi:
17.3 A 28nm 256kb 6T-SRAM with 280mV improvement in VMIN using a dual-split-control assist scheme. ISSCC 2015: 1-3 - [c22]Hiroyuki Yamauchi, Worawit Somha:
Ringing error prevention techniques in Lucy-Richardson deconvolution process for SRAM space-time margin variation effect screening designs. LATS 2015: 1-6 - [c21]Hiroyuki Yamauchi, Worawit Somha:
Feedback gain phase alignment effects on convergence characteristics in Lucy-Richardson deconvolution for inversely predicting complex-shaped RTN distributions. MWSCAS 2015: 1-4 - [c20]Hiroyuki Yamauchi, Worawit Somha:
A Phase Shifting Multiple Filter Design Methodology for Lucy-Richardson Deconvolution of Log-Mixtures Complex RTN Tail Distribution. SBCCI 2015: 20:1-20:6 - [c19]Hiroyuki Yamauchi, Worawit Somha, Yuan-Qiang Song:
A filter design to increase accuracy of Lucy-Richardson deconvolution for analyzing RTN mixtures effects on VLSI reliability margin. SoCC 2015: 121-126 - 2014
- [j25]Worawit Somha, Hiroyuki Yamauchi:
An RTN Variation Tolerant SRAM Screening Test Design with Gaussian Mixtures Approximations of Long-Tail Distributions. J. Electron. Test. 30(2): 171-181 (2014) - [c18]Hiroyuki Yamauchi, Worawit Somha:
A technique to solve issue of Richardson-Lucy deconvolution for analyzing RTN effects on SRAM margin variation. LASCAS 2014: 1-4 - [c17]Hiroyuki Yamauchi, Worawit Somha:
Comparative study on deconvolution function dependencies of RTN/RDF effect estimation errors in analyzing sub-nm-scaled SRAM margins. MWSCAS 2014: 230-233 - [c16]Hiroyuki Yamauchi, Worawit Somha:
Errors in solving inverse problem for reversing RTN effects on VCCmin shift in SRAM reliability screening test designs. SoCC 2014: 318-323 - [c15]Hiroyuki Yamauchi, Worawit Somha:
Deconvolution algorithm dependencies of estimation errors of RTN effects on subnano-scaled SRAM margin variation. VLSI-SoC 2014: 1-6 - 2013
- [j24]Shu-Meng Yang, Meng-Fan Chang, Chi-Chuang Chiang, Ming-Bin Chen, Hiroyuki Yamauchi:
Low-Voltage Embedded NAND-ROM Macros Using Data-Aware Sensing Reference Scheme for VDDmin, Speed and Power Improvement. IEEE J. Solid State Circuits 48(2): 611-623 (2013) - [j23]Meng-Fan Chang, Shin-Jang Shen, Chia-Chi Liu, Che-Wei Wu, Yu-Fan Lin, Ya-Chin King, Chorng-Jung Lin, Hung-Jen Liao, Yu-Der Chih, Hiroyuki Yamauchi:
An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory. IEEE J. Solid State Circuits 48(3): 864-877 (2013) - [j22]Meng-Fan Chang, Chih-Sheng Lin, Wei-Cheng Wu, Ming-Pin Chen, Yen-Huei Chen, Zhe-Hui Lin, Shyh-Shyuan Sheu, Tzu-Kun Ku, Cha-Hsin Lin, Hiroyuki Yamauchi:
A High Layer Scalability TSV-Based 3D-SRAM With Semi-Master-Slave Structure and Self-Timed Differential-TSV for High-Performance Universal-Memory-Capacity-Platforms. IEEE J. Solid State Circuits 48(6): 1521-1529 (2013) - [j21]Meng-Fan Chang, Ming-Bin Chen, Lai-Fu Chen, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, Hsiu-Yun Su, Yuan-Hua Chu, Wen-Chin Wu, Tzu-Yi Yang, Hiroyuki Yamauchi:
A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques. IEEE J. Solid State Circuits 48(10): 2558-2569 (2013) - [c14]Worawit Somha, Hiroyuki Yamauchi:
Convolution/deconvolution SRAM analyses for complex gamma mixtures RTN distributions. ICICDT 2013: 33-36 - [c13]Worawit Somha, Hiroyuki Yamauchi, Ma YuYu:
A discussion on SRAM forward/inverse problem analyses for RTN long-tail distributions. ISVLSI 2013: 58-63 - [c12]Worawit Somha, Hiroyuki Yamauchi:
A RTN variation tolerant guard band design for a deeper nanometer scaled SRAM screening test: Based on EM Gaussians mixtures approximations model of long-tail distributions. LATW 2013: 1-6 - 2012
- [j20]Yen-Huei Chen, Shao-Yu Chou, Quincy Li, Wei-Min Chan, Dar Sun, Hung-Jen Liao, Ping Wang, Meng-Fan Chang, Hiroyuki Yamauchi:
Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM. IEEE J. Solid State Circuits 47(4): 969-980 (2012) - [c11]Meng-Fan Chang, Ching-Hao Chuang, Min-Ping Chen, Lai-Fu Chen, Hiroyuki Yamauchi, Pi-Feng Chiu, Shyh-Shyuan Sheu:
Endurance-aware circuit designs of nonvolatile logic and nonvolatile sram using resistive memory (memristor) device. ASP-DAC 2012: 329-334 - [c10]Ming-Pin Chen, Lai-Fu Chen, Meng-Fan Chang, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, Mon-Shu Ho, Hsiu-Yun Su, Yuan-Hua Chu, Wen-Chin Wu, Tzu-Yi Yang, Hiroyuki Yamauchi:
A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques. VLSIC 2012: 112-113 - 2011
- [j19]Jui-Jen Wu, Yen-Hui Chen, Meng-Fan Chang, Po-Wei Chou, Chien-Yuan Chen, Hung-Jen Liao, Ming-Bin Chen, Yuan-Hua Chu, Wen-Chin Wu, Hiroyuki Yamauchi:
A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme. IEEE J. Solid State Circuits 46(4): 815-827 (2011) - [c9]Meng-Fan Chang, Shin-Jang Shen, Chia-Chi Liu, Che-Wei Wu, Yu-Fan Lin, Shang-Chi Wu, Chia-En Huang, Han-Chao Lai, Ya-Chin King, Chorng-Jung Lin, Hung-Jen Liao, Yu-Der Chih, Hiroyuki Yamauchi:
An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory. ISSCC 2011: 206-208 - 2010
- [j18]Meng-Fan Chang, Jui-Jen Wu, Kuang-Ting Chen, Yung-Chi Chen, Yen-Hui Chen, Robin Lee, Hung-Jen Liao, Hiroyuki Yamauchi:
A Differential Data-Aware Power-Supplied (D 2 AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications. IEEE J. Solid State Circuits 45(6): 1234-1245 (2010) - [j17]Hiroyuki Yamauchi:
A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale Technologies. IEEE Trans. Very Large Scale Integr. Syst. 18(5): 763-774 (2010) - [c8]Meng-Fan Chang, Shu-Meng Yang, Chih-Wei Liang, Chih-Chyuang Chiang, Pi-Feng Chiu, Ku-Feng Lin, Yuan-Hua Chu, Wen-Chin Wu, Hiroyuki Yamauchi:
A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications. ISSCC 2010: 266-267
2000 – 2009
- 2009
- [j16]Yen-Huei Chen, Gary Chan, Shao-Yu Chou, Hsien-Yu Pan, Jui-Jen Wu, Robin Lee, Hung-Jen Liao, Hiroyuki Yamauchi:
A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs. IEEE J. Solid State Circuits 44(4): 1209-1215 (2009) - 2008
- [j15]Toshikazu Suzuki, Hiroyuki Yamauchi, Yoshinobu Yamagami, Katsuji Satomi, Hironori Akamatsu:
A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses. IEEE J. Solid State Circuits 43(9): 2109-2119 (2008) - [j14]Takefumi Yoshikawa, Takashi Hirata, Tsuyoshi Ebuchi, Toru Iwata, Yukio Arima, Hiroyuki Yamauchi:
An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics. IEEE Trans. Very Large Scale Integr. Syst. 16(9): 1187-1198 (2008) - 2007
- [j13]Hiroyuki Yamauchi, Toshikazu Suzuki, Yoshinobu Yamagami:
A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses. IEICE Trans. Electron. 90-C(4): 749-757 (2007) - [j12]Yasue Yamamoto, Masanori Shirahama, Toshiaki Kawasaki, Ryuji Nishihara, Shinichi Sumi, Yasuhiro Agata, Hirohito Kikukawa, Hiroyuki Yamauchi:
A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI. IEICE Trans. Electron. 90-C(5): 1129-1137 (2007) - [c7]Toshikazu Suzuki, Hiroyuki Yamauchi, Katsuji Satomi, Hironori Akamatsu:
A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Biasing Scheme. CICC 2007: 233-236 - [c6]Kevin Zhang, Hiroyuki Yamauchi:
SRAM. ISSCC 2007: 320-321 - [c5]D. P. Wang, Hung-Jen Liao, Hiroyuki Yamauchi, Y. H. Chen, Y. L. Lin, S. H. Lin, D. C. Liu, Huan-Cheng Chang, W. Hwang:
A 45nm dual-port SRAM with write and read capability enhancement at low voltage. SoCC 2007: 211-214 - 2006
- [j11]Hiroyuki Yamauchi, Toshikazu Suzuki, Yoshinobu Yamagami:
A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (Vth) Variation. IEICE Trans. Electron. 89-C(11): 1526-1534 (2006) - [j10]Toshikazu Suzuki, Yoshinobu Yamagami, Ichiro Hatanaka, Akinori Shibayama, Hironori Akamatsu, Hiroyuki Yamauchi:
A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme. IEEE J. Solid State Circuits 41(1): 152-160 (2006) - 2005
- [j9]Toshikazu Suzuki, Yoshinobu Yamagami, Ichiro Hatanaka, Akinori Shibayama, Hironori Akamatsu, Hiroyuki Yamauchi:
0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier. IEICE Trans. Electron. 88-C(4): 630-638 (2005) - [j8]Masanori Shirahama, Yasuhiro Agata, Toshiaki Kawasaki, Ryuji Nishihara, Wataru Abe, Naoki Kuroda, Hiroyuki Sadakata, Toshitaka Uchikoba, Kazunari Takahashi, Kyoko Egashira, Shinji Honda, Miho Miura, Shin Hashimoto, Hirohito Kikukawa, Hiroyuki Yamauchi:
A 400-MHz random-cycle dual-port interleaved DRAM (D2RAM) with standard CMOS Process. IEEE J. Solid State Circuits 40(5): 1200-1207 (2005) - [j7]Masahisa Iida, Naoki Kuroda, Hidefumi Otsuka, Masanobu Hirose, Yuji Yamasaki, Kiyoto Ohta, Kazuhiko Shimakawa, Takashi Nakabayashi, Hiroyuki Yamauchi, Tomohiko Sano, Takayuki Gyohten, Masanao Maruta, Akira Yamazaki, Fukashi Morishita, Katsumi Dosaka, Masahiko Takeuchi, Kazutami Arimoto:
A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning. IEEE J. Solid State Circuits 40(11): 2296-2304 (2005) - 2000
- [c4]Hiroyuki Yamauchi, Setsuo Ohsuga:
A Method and Language for Constructing Multiagent Systems. ISMIS 2000: 619-628
1990 – 1999
- 1999
- [c3]Hiroyuki Yamauchi, Setsuo Ohsuga:
Incorporating Fuzzy Set Theory and Matrix Logic in Multi-Layer Logic - A Preliminary Consideration. RSFDGrC 1999: 304-313 - 1997
- [j6]Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa:
A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture. IEEE Trans. Very Large Scale Integr. Syst. 5(4): 377-387 (1997) - 1996
- [j5]Hiroyuki Yamauchi, Akira Matsuzawa:
A signal-swing suppressing strategy for power and layout area savings using time-multiplexed differential data-transfer scheme. IEEE J. Solid State Circuits 31(9): 1285-1294 (1996) - [c2]Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa:
A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes. ISLPED 1996: 49-54 - 1995
- [j4]Hiroyuki Yamauchi, Hironori Akamatsu, Tsutomu Fujita:
An asymptotically zero power charge-recycling bus architecture for battery-operated ultrahigh data rate ULSI's. IEEE J. Solid State Circuits 30(4): 423-431 (1995) - [j3]Hiroyuki Yamauchi, Tom Iwata, Akito Uno, Masanori Fukumoto, Tsutomu Fujita:
A circuit technology for a self-refresh 16 Mb DRAM with less than 0.5 μA/MB data-retention current. IEEE J. Solid State Circuits 30(11): 1174-1182 (1995) - 1990
- [j2]Hiroyuki Yamauchi, Setsuo Ohsuga:
Losse Coupling of KAUS with Existing RDBMSs. Data Knowl. Eng. 5: 227-251 (1990)
1980 – 1989
- 1985
- [j1]Setsuo Ohsuga, Hiroyuki Yamauchi:
Multi-Layer Logic - A Predicate Logic Including Data Structure as Knowledge Representation Language. New Gener. Comput. 3(4): 403-439 (1985) - 1980
- [c1]Hiroyuki Yamauchi:
Processing Of Syntax And Semantics Of Natural Language By Predicate Logic Of Predicate Logic. COLING 1980: 389-396
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-08-05 20:25 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
