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ORCIDYukio Arima
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2000 – 2009
- 2009
[j5]Tsuyoshi Ebuchi, Yoshihide Komatsu, Tatsuo Okamoto, Yukio Arima, Yuji Yamada, Kazuaki Sogawa, Kouji Okamoto, Takashi Morie, Takashi Hirata, Shiro Dosho, Takefumi Yoshikawa:
A 125-1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration. IEEE J. Solid State Circuits 44(3): 763-774 (2009)- 2008
- [j4]Takefumi Yoshikawa, Takashi Hirata, Tsuyoshi Ebuchi, Toru Iwata, Yukio Arima, Hiroyuki Yamauchi
:
An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics. IEEE Trans. Very Large Scale Integr. Syst. 16(9): 1187-1198 (2008) - 2006
- [j3]Koichiro Ishibashi, Tetsuya Fujimoto, Takahiro Yamashita, Hiroyuki Okada, Yukio Arima, Yasuyuki Hashimoto, Kohji Sakata, Isao Minematsu, Yasuo Itoh, Haruki Toda, Motoi Ichihashi, Yoshihide Komatsu, Masato Hagiwara, Toshiro Tsukada:
Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond. IEICE Trans. Electron. 89-C(3): 250-262 (2006) - [j2]Yoshihide Komatsu, Yukio Arima, Koichiro Ishibashi:
Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond. IEICE Trans. Electron. 89-C(3): 384-391 (2006) - 2005
- [j1]Takefumi Yoshikawa, Tsuyoshi Ebuchi, Yukio Arima, Toru Iwata:
A Spread Spectrum Clock Generator Using Digital Tracking Scheme. IEICE Trans. Electron. 88-C(6): 1288-1289 (2005) - 2004
- [c1]Yoshihide Komatsu, Yukio Arima, Tetsuya Fujimoto, Takahiro Yamashita, Koichiro Ishibashi:
A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond. CICC 2004: 329-332
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