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ORCIDToshikazu Suzuki
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2010 – 2019
- 2014
[j12]Yuichi Miyahara, Mitsuhiro Sano, Kazuo Koyama, Toshikazu Suzuki, Koichi Hamashita, Bang-Sup Song:
A 14b 60 MS/s Pipelined ADC Adaptively Cancelling Opamp Gain and Nonlinearity. IEEE J. Solid State Circuits 49(2): 416-425 (2014)- 2013
- [j11]Shinji Miyano, Shinichi Moriwaki, Yasue Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Hirofumi Shinohara:
Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges. IEEE J. Solid State Circuits 48(4): 924-931 (2013) - [j10]Kousuke Miyaji, Toshikazu Suzuki, Shinji Miyano, Ken Takeuchi:
A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy. IEEE J. Solid State Circuits 48(9): 2239-2249 (2013) - [c13]Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi
, Masahiko Yoshimoto:
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique. ASP-DAC 2013: 77-78 - [c12]Yuichi Miyahara, Mitsuhiro Sano, Kazuo Koyama, Toshikazu Suzuki, Koichi Hamashita, Bang-Sup Song:
Adaptive cancellation of gain and nonlinearity errors in pipelined ADCs. ISSCC 2013: 282-283 - 2012
- [j9]Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique. IEICE Electron. Express 9(12): 1023-1029 (2012) - [j8]Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme. IEICE Trans. Electron. 95-C(4): 572-578 (2012) - [c11]Yasue Yamamoto, Atsushi Kawasumi, Shinichi Moriwaki, Toshikazu Suzuki, Shinji Miyano, Hirofumi Shinohara:
60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations. ESSCIRC 2012: 317-320 - [c10]Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. ISLPED 2012: 85-90 - [c9]Masaharu Terada, Shusuke Yoshimoto, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction. ISQED 2012: 489-492 - [c8]Kousuke Miyaji, Toshikazu Suzuki, Shinji Miyano, Ken Takeuchi:
A 6T SRAM with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energy. ISSCC 2012: 232-234 - [c7]Shinichi Moriwaki, Yasuhiro Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Shinji Miyano, Takayasu Sakurai, Hirofumi Shinohara:
A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges. VLSIC 2012: 60-61 - 2011
- [c6]Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano:
Energy efficiency degradation caused by random variation in low-voltage SRAM and 26% energy reduction by Bitline Amplitude Limiting (BAL) scheme. A-SSCC 2011: 165-168 - [c5]Shinichi Moriwaki, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Shinji Miyano:
0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme. CICC 2011: 1-4 - 2010
- [c4]Toshikazu Suzuki, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara:
0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme. ESSCIRC 2010: 354-357
2000 – 2009
- 2008
- [j7]Toshikazu Suzuki, Hiroyuki Yamauchi, Yoshinobu Yamagami, Katsuji Satomi, Hironori Akamatsu:
A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses. IEEE J. Solid State Circuits 43(9): 2109-2119 (2008) - 2007
- [j6]Hiroyuki Yamauchi, Toshikazu Suzuki, Yoshinobu Yamagami:
A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses. IEICE Trans. Electron. 90-C(4): 749-757 (2007) - [c3]Toshikazu Suzuki, Hiroyuki Yamauchi, Katsuji Satomi, Hironori Akamatsu:
A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Biasing Scheme. CICC 2007: 233-236 - 2006
- [j5]Hiroyuki Yamauchi, Toshikazu Suzuki, Yoshinobu Yamagami:
A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (Vth) Variation. IEICE Trans. Electron. 89-C(11): 1526-1534 (2006) - [j4]Toshikazu Suzuki, Yoshinobu Yamagami, Ichiro Hatanaka, Akinori Shibayama, Hironori Akamatsu, Hiroyuki Yamauchi:
A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme. IEEE J. Solid State Circuits 41(1): 152-160 (2006) - 2005
- [j3]Toshikazu Suzuki, Yoshinobu Yamagami, Ichiro Hatanaka, Akinori Shibayama, Hironori Akamatsu, Hiroyuki Yamauchi:
0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier. IEICE Trans. Electron. 88-C(4): 630-638 (2005) - 2004
- [j2]Koji Nii, Yasumasa Tsukamoto, Tomoaki Yoshizawa, Susumu Imaoka, Yoshinobu Yamagami, Toshikazu Suzuki, Akinori Shibayama, Hiroshi Makino, Shuhei Iwade:
A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications. IEEE J. Solid State Circuits 39(4): 684-693 (2004) - 2003
- [c2]Xiaoyang Mao, Toshikazu Suzuki, Atsumi Imamiya:
AtelierM: a physically based interactive system for creating traditional marbling textures. GRAPHITE 2003: 79-86 - 2001
- [c1]Toshikazu Suzuki, Xiaoyang Mao, Atsumi Imamiya:
Simulating Marbling with Computer Graphics. VIIP 2001: 208-213
1990 – 1999
- 1994
- [j1]Toshikazu Suzuki:
ATM adaptation layer protocol. IEEE Commun. Mag. 32(4): 80-83 (1994)
Coauthor Index
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