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ISQED 2009: San Jose, California, USA
- 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA. IEEE Computer Society 2009, ISBN 978-1-4244-2952-3
Aging Aware Design
- Adam C. Cabe, Zhenyu Qi, Stuart N. Wooters, Travis N. Blalock, Mircea R. Stan
:
Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay. 1-6 - Chenyue Ma, Bo Li, Lining Zhang, Jin He, Xing Zhang, Xinnan Lin, Mansun Chan
:
A unified FinFET reliability model including high K gate stack dynamic threshold voltage, hot carrier injection, and negative bias temperature instability. 7-12 - Balaji Vaidyanathan, Anthony S. Oates, Yuan Xie, Yu Wang
:
NBTI-aware statistical circuit delay assessment. 13-18 - Yu Wang
, Xiaoming Chen, Wenping Wang, Varsha Balakrishnan, Yu Cao
, Yuan Xie, Huazhong Yang:
On the efficacy of input Vector Control to mitigate NBTI effects and leakage power. 19-26
Robust Circuits
- R. Venkatraman, R. Castagnetti, Andres Teene, Benjamin Mbouombouo, S. Ramesh:
Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design. 27-32 - Hariharan Sankaran, Srinivas Katkoori
:
On-chip dynamic worst-case crosstalk pattern detection and elimination for bus-based macro-cell designs. 33-39 - Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti
, Yu Hu:
Worst case timing jitter and amplitude noise in differential signaling. 40-46 - Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos, Priyadarsan Patra
:
A PVT aware accurate statistical logic library for high- metal-gate nano-CMOS. 47-54
Library & Modeling
- Xin Wang, Alireza Kasnavi, Harold Levy:
A general piece-wise nonlinear library modeling format and size reduction technique for gate-level timing, SI, power, and variation analysis. 55-61 - Chandra S. Nagarajan, Lin Yuan, Gang Qu, Barbara G. Stamps:
Leakage optimization using transistor-level dual threshold voltage cell library. 62-67 - Chun-Yu Chuang, Wai-Kei Mak:
Accurate closed-form parameterized block-based statistical timing analysis applying skew-normal distribution. 68-73 - Savithri Sundareswaran, Rajendran Panda, Jacob A. Abraham, Yun Zhang, Amit Mittal:
Characterization of sequential cells for constraint sensitivities. 74-79
Design & Modeling in Emerging Technologies
- Charles Augustine, Arijit Raychowdhury, Yunfei Gao, Mark S. Lundstrom, Kaushik Roy:
PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices. 80-85 - Rakesh S. Anigundi, Hongbin Sun, Jian-Qiang Lu, Kenneth Rose, Tong Zhang:
Architecture design exploration of three-dimensional (3D) integrated DRAM. 86-90 - Jeremy R. Tolbert, Saibal Mukhopadhyay:
Accurate buffer modeling with slew propagation in subthreshold circuits. 91-96 - Bao Liu:
Robust differential asynchronous nanoelectronic circuits. 97-102
Circuits for Noise and Variation Tolerance
- Karthik Rajagopal, Aatmesh, Vinod Menezes:
An enhanced topology for reliability of a high performance 3.3V I/O buffer in a single-well bulk CMOS 1.8v-oxide low voltage process. 103-106 - Soheil Ziabakhsh, Hosein Alavi-Rad
, Mohammad Alavi-Rad, Mohammad Mortazavi:
The design of a low-power high-speed current comparator in 0.35-m CMOS technology. 107-111 - Wai Leng Cheong, Brian E. Owens, Hui En Pham, Christopher Hanken, Jim Le, Terri S. Fiez, Kartikeya Mayaram:
Comparison of supply noise and substrate noise reduction in SiGe BiCMOS and FDSOI processes. 112-115 - Charbel J. Akl, Rafic A. Ayoubi, Magdy A. Bayoumi:
An effective staggered-phase damping technique for suppressing power-gating resonance noise during mode transition. 116-119
Power vs Performance Trade offs
- Ehsan Pakbaznia, Massoud Pedram:
Design and application of multimodal power gating structures. 120-126 - Kwangok Jeong, Andrew B. Kahng, Hailong Yao:
Revisiting the linear programming framework for leakage power vs. performance optimization. 127-134 - António Gusmão, L. Miguel Silveira
, José Monteiro
:
Parameter tuning in SVM-based power macro-modeling. 135-140 - Ying-Cherng Lan, Michael C. Chen, Wei-De Chen, Sao-Jie Chen
, Yu Hen Hu:
Performance-energy tradeoffs in reliable NoCs. 141-146
Process Variation
- Siddharth Garg, Diana Marculescu
:
3D-GCP: An analytical model for the impact of process variations on the critical path delay distribution of 3D ICs. 147-155 - Valeriy Sukharev
, Ara Markosian, Armen Kteyan, Levon Manukyan, Nikolay Khachatryan, Jun-Ho Choy, Hasmik Lazaryan, Henrik Hovsepyan, Seiji Onoue, Takuo Kikuchi, Tetsuya Kamigaki:
Control of design specific variation in etch-assisted via pattern transfer by means of full-chip simulation. 156-161 - Farshad Moradi
, Dag T. Wisland, Hamid Mahmoodi
, Ali Peiravi
, Snorre Aunet, Tuan Vu Cao:
New subthreshold concepts in 65nm CMOS technology. 162-166 - Simeon Realov, William F. McLaughlin, Kenneth L. Shepard:
On-chip transistor characterization arrays with digital interfaces for variability characterization. 167-171
Embedded Papers
- Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos:
Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments. 172-178 - Jwu-E Chen, Pei-Wen Luo, Chin-Long Wey:
Yield evaluation of analog placement with arbitrary capacitor ratio. 179-184 - Aditya P. Karmarkar, Xiaopeng Xu, Victor Moroz, Greg Rollins, Xiao Lin:
Analysis of performance and reliability trade-off in dummy pattern design for 32-nm technology. 185-189 - Rouwaida Kanj, Rajiv V. Joshi, Jente B. Kuang, J. Kim, Mesut Meterelliyoz, William R. Reohr, Sani R. Nassif, Kevin J. Nowka
:
Statistical yield analysis of silicon-on-insulator embedded DRAM. 190-194 - Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera:
Erect of regularity-enhanced layout on printability and circuit performance of standard cells. 195-200 - Enric Musoll:
Trading off higher execution latency for increased reliability in tile-based massive multi-core architectures. 201-207 - Yan Liu, Scott Hareland, Donald Hall, Bill Wold, Roger Hubing, Robert Mehregan, Ronen Malka, Manish Sharma, Tom Lane:
A Simulation-based strategy used in electrical design for reliability. 208-212 - Satish Sivaswamy, Kia Bazargan, Marc D. Riedel
:
Estimation and optimization of reliability of noisy digital circuits. 213-219 - Biwei Liu, Shuming Chen, Yi Xu:
Combinational logic SER estimation with the presence of re-convergence. 220-225 - Jone F. Chen, Kuen-Shiuan Tian, Shiang-Yu Chen, Kuo-Ming Wu, C. M. Liu:
Effect of NDD dosage on hot-carrier reliability in DMOS transistors. 226-229 - Amir Khatib Zadeh, Catherine H. Gebotys:
Side channel aware leakage management in nanoscale Cryptosystem-on-Chip (CoC). 230-235 - Hai Yu, Michael Nicolaidis, Lorena Anghel
:
An effective approach to detect logic soft errors in digital circuits based on GRAAL. 236-240 - Meng-Syue Chan, Chun-Yao Wang, Yung-Chih Chen:
An efficient approach to sip design integration. 241-247 - Bin Zhou, Yizheng Ye, Zhao-lin Li, Xin-chun Wu, Rui Ke:
A new low power test pattern generator using a variable-length ring counter. 248-252 - Youssef Benabboud, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
, Laroussi Bouzaida, Isabelle Izaute:
A case study on logic diagnosis for System-on-Chip. 253-259 - Anshuman Chandra, Yasunari Kanzawa, Rohit Kapur:
Proactive management of X's in scan chains for compression. 260-265 - Hsiu-Ming Chang, Kuan-Yu Lin, Chin-Hsuan Chen, Kwang-Ting Cheng
:
A Built-in self-calibration scheme for pipelined ADCs. 266-271 - Bing-Wei Huang, Jin-Fu Li:
Efficient diagnosis algorithms for drowsy SRAMs. 276-279 - Yuchun Ma, Xiang Qiu, Xiangqing He, Xianlong Hong:
Incremental power optimization for multiple supply voltage design. 280-286 - Yun Du, Yangshuo Ding, Yujie Chen, Zhiqiang Gao:
IP protection platform based on watermarking technique. 287-290 - Mohsen Raji
, Behnam Ghavami, Hossein Pedram:
Statistical static performance analysis of asynchronous circuits considering process variation. 291-296 - Lei Gao, David Zaretsky, Gaurav Mittal, Dan Schonfeld, Prith Banerjee:
A software pipelining algorithm in high-level synthesis for FPGA architectures. 297-302 - Qian Ying Tang, Qiang Chen, Niloy Chatterjee, Vedank Tripathi, Natarajan Nandagopalan, Sridhar Tirumala:
Phenomenological model for gate length bias dependent inverter delay change with emphasis on library characterization. 303-308 - Thom Jefferson A. Eguia, Ning Mi, Sheldon X.-D. Tan:
Statistical decoupling capacitance allocation by efficient numerical quadrature method. 309-316 - Yi-Ling Liu, Chun-Yao Wang, Yung-Chih Chen, Ya-Hsin Chang:
A novel ACO-based pattern generation for peak power estimation in VLSI circuits. 317-323 - Leomar S. da Rosa Jr., Felipe Ribeiro Schneider, Renato P. Ribas, André Inácio Reis:
Switch level optimization of digital CMOS gate networks. 324-329
System Level Modeling & Design
- Muhammad Rashid
, Fabrizio Ferrandi
, Koen Bertels:
hArtes design flow for heterogeneous platforms. 330-338 - Adeel Israr, Abdulhadi Shoufan
, Sorin A. Huss:
An efficient reliability evaluation approach for system-level design of embedded systems. 339-344 - Feng Liu, Otmane Aït Mohamed, Xiaoyu Song, QingPing Tan:
A case study on system-level modeling by aspect-oriented programming. 345-349 - Amlan Ganguly, Kevin Chang, Partha Pratim Pande, Benjamin Belzer, Alireza Nojeh
:
Performance evaluation of wireless networks on chip architectures. 350-355
System and Interface Validation
- Albert Chiang, Wei-Hua Han, Bhanu Kapoor:
Validating physical access layer of WiMAX using SystemVerilog. 356-359 - Yongquan Fan, Zeljko Zilic:
Accelerating jitter tolerance qualification for high speed serial interfaces. 360-365 - Hiroaki Yoshida, Masahiro Fujita:
Improving the accuracy of rule-based equivalence checking of system-level design descriptions by identifying potential internal equivalences. 366-370 - Miroslav N. Velev
, Ping Gao:
Efficient SAT-based techniques for Design of Experiments by using static variable ordering. 371-376 - Mrinal Bose, Prashant Naphade, Jayanta Bhadra, Hillel Miller:
An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCs. 377-381
Quality Digital Design
- Javid Jaffari, Mohab Anis:
Timing yield estimation of digital circuits using a control variate technique. 382-387 - Koustav Bhattacharya, Nagarajan Ranganathan:
A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations. 388-393 - Stephen Bijansky, Sae Kyu Lee, Adnan Aziz:
TuneLogic: Post-silicon tuning of dual-Vdd designs. 394-400 - Shingo Watanabe, Masanori Hashimoto
, Toshinori Sato
:
A case for exploiting complex arithmetic circuits towards performance yield enhancement. 401-407 - Natasa Miskov-Zivanov, Diana Marculescu
:
A systematic approach to modeling and analysis of transient faults in logic circuits. 408-413
Embedded Papers
- Thorsten Weyl, Dave Clarke, Karl Rinne, James A. Power:
ESD event simulation automation using automatic extraction of the relevant portion of a full chip. 414-418 - Ayhan A. Mutlu, Jiayong Le, Ruben Molina, Mustafa Celik:
Parametric analysis to determine accurate interconnect extraction corners for design performance. 419-423 - Shu Li, Tong Zhang:
Exploratory study on circuit and architecture design of very high density diode-switch phase change memories. 424-429 - Bao Liu:
Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolution. 430-435 - Anita Kumari, Javier F. Pulecio, Sanjukta Bhanja:
Defect characterization in magnetic field coupled arrays. 436-441 - Akif Sultan, John Faricelli, Sushant Suryagandh, Hans vanMeer, Kaveri Mathur, James Pattison, Sean Hannon, Greg Constant, Kalyana Kumar, Kevin Carrejo, Joe Meier, Rasit Onur Topaloglu
, Darin Chan, Uwe Hahn, Thorsten Knopp, Victor Andrade, Bill Gardiol, Steve Hejl, David Wu, James Buller, Larry Bair, Ali Icel, Yuri Apanovich:
CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design. 442-446 - Maruthi Chandrasekhar Bh, Sudeb Dasgupta:
A 1.2 volt, 90nm, 16-bit three way segmented digital to analog converter (DAC) for low power applications. 447-450 - Yulei Zhang, Ling Zhang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng:
Design methodology of high performance on-chip global interconnect using terminated transmission-line. 451-458 - Ji-Hye Bong, Yong-Jin Kwon, Kyeong-Sik Min, Sung-Mo Kang:
New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMs. 459-464 - Xin He, Syed Al-Kadry, Afshin Abdollahi:
Adaptive leakage control on body biasing for reducing power consumption in CMOS VLSI circuit. 465-470 - S. Lakshminarayanan, J. Joung, Giri Narasimhan
, Ravi Kapre, M. Slanina, J. Tung, Morgan Whately, C.-L. Hou, W.-J. Liao, S.-C. Lin, P.-G. Ma, C.-W. Fan, M.-C. Hsieh, F.-C. Liu, K.-L. Yeh, W.-C. Tseng, S. W. Lu:
Standby power reduction and SRAM cell optimization for 65nm technology. 471-475 - Parimala Viswanath, Pranav Murthy, Debajit Das, R. Venkatraman, Ajoy Mandal, Arvind Veeravalli, H. Udayakumar:
Optimization strategies to improve statistical timing. 476-481 - Jithendra Srinivas, Madhusudan Rao, Sukumar Jairam, H. Udayakumar, Jagdish C. Rao:
Clock gating effectiveness metrics: Applications to power optimization. 482-487 - Hsin-Hua Pan, Hung-Ming Chen, Chia-Yi Chang:
Buffer/flip-flop block planning for power-integrity-driven floorplanning. 488-493 - Basab Datta, Wayne P. Burleson:
On temperature planarization effect of copper dummy fills in deep nanometer technology. 494-499 - Uday Doddannagari, Shiyan Hu, Weiping Shi:
Fast characterization of parameterized cell library. 500-505 - Dawei Liu, Qiang Zhou, Jinian Bian, Yici Cai, Xianlong Hong:
Cell shifting aware of wirelength and overlap. 506-510 - Mei-Fang Chiang, Takumi Okamoto, Takeshi Yoshimura:
Lagrangian relaxation based register placement for high-performance circuits. 511-516 - Adithya V. Kodati, Koneswara S. Vemuri, Lili He, Morris Jones:
Implementation of power managed hyper transport system for transmission of HD video. 517-521 - Zohreh Karimi, Majid Sarrafzadeh:
Power aware placement for FPGAs with dual supply voltages. 522-526 - Saraju P. Mohanty, Elias Kougianos, Wei Cai, Manish Ratnani:
VLSI architectures of perceptual based video watermarking for real-time copyright protection. 527-534 - Shu-Hsuan Chou, Chi-Neng Wen, Yan-Ling Liu, Tien-Fu Chen:
VeriC: A semi-hardware description language to bridge the gap between ESL design and RTL models. 535-540 - Sumit Ahuja, Deepak Mathaikutty, Gaurav Singh, Joe Stetzer, Sandeep K. Shukla
, Ajit Dingankar:
Power estimation methodology for a high-level synthesis framework. 541-546 - Miguel Miranda, Bart Dierickx
, Paul Zuber, Petr Dobrovolný, F. Kutscherauer, Philippe Roussel, Pavel Poliakov:
Variability aware modeling of SoCs: From device variations to manufactured system yield. 547-553 - Hailong You, Maofeng Yang, Dan Wang, Xinzhang Jia:
Kriging Model combined with latin hypercube sampling for surrogate modeling of analog integrated circuit performance. 554-558
Co design applications for IC Packaging
- Joseph Fjelstad:
Retrospective on electronics technology and prospective methods for co-design of IC packaging and manufacturing improvements. 559-564 - Farhang Yazdani, Jamal S. Izadian:
50GB/s signaling on organic substrates using PMTL technology. 565-568 - Syed M. Alam, Robert E. Jones, Scott Pozder, Ankur Jain:
Die/wafer stacking with reciprocal design symmetry (RDS) for mask reuse in three-dimensional (3D) integration technology. 569-575 - Amirali Shayan Arani, Xiang Hu, He Peng, Wenjian Yu, Wanping Zhang, Chung-Kuan Cheng, Mikhail Popovich, Xiaoming Chen, Lew Chua-Eoan, Xiaohua Kong:
Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network. 576-581
Novel Design Methodologies
- Lining Zhang, Jin He, Jian Zhang, Feng Liu, Yue Fu, Yan Song, Xing Zhang:
An analytic model for Ge/Si core/shell nanowire MOSFETs considering drift-diffusion and ballistic transport. 582-587 - Vinayak Honkote, Baris Taskin:
Zero clock skew synchronization with rotary clocking technology. 588-593 - Kevin Brownell, Ali Durlov Khan, David M. Brooks, Gu-Yeon Wei:
Place and route considerations for voltage interpolated designs. 594-600 - Genichi Tanaka, Koichi Nakashiro:
Crosstalk pessimism reduction with path base analysis. 601-606
Memory Design Solutions
- Nancy Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi:
The impact of BEOL lithography effects on the SRAM cell performance and yield. 607-612 - Yanzhong Xu, Lin-Shih Liu, Mark Chan, Jeff Watt:
Process variation impact on FPGA configuration memory. 613-616 - Soner Yaldiz, Umut Arslan, Xin Li, Larry T. Pileggi:
Efficient statistical analysis of read timing failures in SRAM circuits. 617-621 - Costas Argyrides, Ahmad A. Al-Yamani, Carlos Arthur Lang Lisbôa, Luigi Carro
, Dhiraj K. Pradhan:
Increasing memory yield in future technologies through innovative design. 622-626
Clock and Noise
- Debasish Das, William Scott, Shahin Nazarian, Hai Zhou:
An efficient current-based logic cell model for crosstalk delay analysis. 627-633 - Xiaoji Ye, Peng Li:
An application-specific adjoint sensitivity analysis framework for clock mesh sensitivity computation. 634-640 - Ramamurthy Vishweshwara, Ramakrishnan Venkatraman, Vipul Kadodwala:
Early clock prototyping for design analysis and quality entitlement. 641-646 - Wenting Hou, Dick Liu, Pei-Hsin Ho:
Automatic register banking for low-power clock trees. 647-652 - Aida Todri
, Malgorzata Marek-Sadowska, Francois Maire, Christophe Matheron:
A study of decoupling capacitor effectiveness in power and ground grid networks. 653-658
Low Voltage Design
- Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi
, Masahiko Yoshimoto:
A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme. 659-663 - Suganth Paul, Rajesh Garg, Sunil P. Khatri, Sheila Vaidya:
Design and implementation of a sub-threshold BFSK transmitter. 664-672 - Saraju P. Mohanty, Dhruva Ghai, Elias Kougianos, Bharat Joshi:
A universal level converter towards the realization of energy efficient implantable drug delivery Nano-Electro-Mechanical-Systems. 673-679 - Basab Datta, Wayne P. Burleson:
Temperature effects on energy optimization in sub-threshold circuit design. 680-685 - Amir Moradi
, Mehrdad Khatir, Mahmoud Salmasizadeh, Mohammad T. Manzuri Shalmani:
Charge recovery logic as a side channel attack countermeasure. 686-691
Test Power and Noise
- Bhanu Kapoor, Shankar Hemmady, Shireesh Verma, Kaushik Roy, Manuel A. d'Abreu:
Impact of SoC power management techniques on verification and testing. 692-695 - Alodeep Sanyal, Abhisek Pan, Sandip Kundu:
A study on impact of loading effect on capacitive crosstalk noise. 696-701 - Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He:
Simultaneous test pattern compaction, ordering and X-filling for testing power reduction. 702-707 - Aftab Farooqi, Richard O. Gale, Sudhakar M. Reddy, Brian Nutter
, Chris Monico:
Markov source based test length optimized SCAN-BIST architecture. 708-713 - Alexander L. Stempkovsky
, Alexey Glebov, Sergey Gavrilov
:
Calculation of stress probability for NBTI-aware timing analysis. 714-718
Advances in timing Analysis and floor planning
- Ali Dasdan, Santanu Kolay, Mustafa Yazgan:
Derating for static timing analysis: Theory and practice. 719-727 - Nikolay Rubanov:
An information theoretic framework to compute the MAX/MIN operations in parameterized statistical timing analysis. 728-733 - Song Chen
, Zheng Xu, Takeshi Yoshimura:
A generalized V-shaped multilevel method for large scale floorplanning. 734-739 - Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong:
Simultaneous buffer and interlayer via planning for 3D floorplanning. 740-745 - Akhilesh Kumar, Mohab Anis:
IR-drop management CAD techniques in FPGAs for power grid reliability. 746-752
Power Analysis and Power Delivery Systems
- Sriram Sambamurthy, Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham:
Functionally valid gate-level peak power estimation for processors. 753-758 - Jonathan Rosenfeld, Eby G. Friedman:
On-chip DC-DC converters for three-dimensional ICs. 759-764 - Xiongfei Meng, Resve A. Saleh:
Active decap design considerations for optimal supply noise reduction. 765-769 - Shan Zeng, Wenjian Yu, Wanping Zhang, Jian Wang, Xianlong Hong, Chung-Kuan Cheng:
Efficient power network analysis with complete inductive modeling. 770-775 - Zhiyu Zeng, Peng Li, Zhuo Feng:
Parallel partitioning based on-chip power distribution network analysis using locality acceleration. 776-781
Low Voltage and Variation-Tolerant Design
- Animesh Kumar, Jan M. Rabaey, Kannan Ramchandran:
SRAM supply voltage scaling: A reliability perspective. 782-787 - Seung Eun Lee, Chris Wilkerson, Ming Zhang, Rajendra S. Yavatkar, Shih-Lien Lu, Nader Bagherzadeh
:
Low power adaptive pipeline based on instruction isolation. 788-793 - Charbel J. Akl, Rafic A. Ayoubi, Magdy A. Bayoumi:
Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networks. 794-798 - Ashay Narsale, Michael C. Huang
:
Variation-tolerant hierarchical voltage monitoring circuit for soft error detection. 799-805 - Rajballav Dash, Rajesh Garg, Sunil P. Khatri, Gwan S. Choi:
SEU hardened clock regeneration circuits. 806-813
System Power and Reliability
- Sohaib Majzoub
, Resve A. Saleh, Rabab K. Ward:
PVT variation impact on voltage island formation in MPSoC design. 814-819 - Toshinori Sato
, Shingo Watanabe:
Uncriticality-directed scheduling for tackling variation and power challenges. 820-825 - Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang:
Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs). 826-832 - Jin Sun, Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang:
NBTI aware workload balancing in multi-core systems. 833-838 - Mehrtash Manoochehri, Alireza Ejlali, Seyed Ghassem Miremadi:
Joint write policy and fault-tolerance mechanism selection for caches in DSM technologies: Energy-reliability trade-off. 839-844
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