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ORCIDH. Udayakumar
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2000 – 2009
- 2009
[c13]Parimala Viswanath, Pranav Murthy, Debajit Das, R. Venkatraman, Ajoy Mandal, Arvind Veeravalli, H. Udayakumar:
Optimization strategies to improve statistical timing. ISQED 2009: 476-481- [c12]Jithendra Srinivas, Madhusudan Rao, Sukumar Jairam, H. Udayakumar, Jagdish C. Rao:
Clock gating effectiveness metrics: Applications to power optimization. ISQED 2009: 482-487 - [c11]Ramamurthy Vishweshwara, Ramakrishnan Venkatraman, H. Udayakumar, N. V. Arvind:
An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis. VLSI Design 2009: 519-524 - 2008
- [c10]Sukumar Jairam, Madhusudan Rao, Jithendra Srinivas, Parimala Vishwanath, H. Udayakumar, Jagdish C. Rao:
Clock gating for power optimization in ASIC design cycle theory & practice. ISLPED 2008: 307-308 - [c9]Sukumar Jairam, S. M. Stalin, Jean-Yves Oberle, H. Udayakumar:
An SSO Based Methodology for EM Emission Estimation from SoCs. ISQED 2008: 297-300 - [c8]Ajit Gupte, Mohit Sharma, Gaurav Varshney, Lakshmikantha Holla, Parvinder Rana, H. Udayakumar:
Memory Power Modeling - A Novel Approach. ISVLSI 2008: 263-268 - 2006
- [c7]Snehashis Roy
, Sukumar Jairam, H. Udayakumar:
A Methodology for Switching Activity Based IO Powerpad Optimisation. VLSI Design 2006: 794-797 - 2005
- [c6]Sankar P. Debnath, Sukumar Jairam, H. Udayakumar:
A Methodology for Fast Vector Based Power Supply and Substrate Noise Analyses. VLSI Design 2005: 808-811 - 2004
- [c5]P. R. Suresh, P. K. Sundararajan, Anshuli Goel, H. Udayakumar, C. Srinivasan, Vasudev Sinari, Raghavendrakumar Ravinutala:
Package-silicon co-design - Experiment with an SOC design. VLSI Design 2004: 531- - 2002
- [c4]Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji:
Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon. ASP-DAC/VLSI Design 2002: 781-788 - 2000
- [c3]Karthikeyan Madathil, Jagdish C. Rao, Subash Chandar G., Amitabh Menon, Avinash K. Gautam, Amit M. Brahme, H. Udayakumar:
A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores. VLSI Design 2000: 468-
1990 – 1999
- 1999
- [c2]Avinash K. Gautam, Jagdish C. Rao, Karthikeyan Madathil, Vilesh Shah, H. Udayakumar, Amitabh Menon, Subash Chandar G.:
A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology. ICCD 1999: 340-347 - [c1]Avinash K. Gautam, Jagdish C. Rao, Rohit Rathi, H. Udayakumar:
A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors. VLSI Design 1999: 346-349
Coauthor Index
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